Changeset ffc277e in mainline for arch/mips/src
- Timestamp:
- 2005-09-10T00:52:13Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f3a6c8e5
- Parents:
- b02e5d1
- Location:
- arch/mips/src
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/mips/src/asm.S
rb02e5d1 rffc277e 27 27 # 28 28 29 #include <arch/asm/regname.h> 30 29 31 .text 30 32 … … 116 118 117 119 118 .global tlbp119 tlbp:120 tlbp121 j $31122 nop123 124 .global tlbr125 tlbr:126 tlbr127 j $31128 nop129 130 .global tlbwi131 tlbwi:132 tlbwi133 j $31134 nop135 136 .global tlbwr137 tlbwr:138 tlbwr139 j $31140 nop141 142 120 .global cpu_halt 143 121 cpu_halt: … … 156 134 nop 157 135 136 .macro fpu_gp_save reg ctx 137 mfc1 $t0,$\reg 138 sw $t0, \reg*4(\ctx) 139 .endm 140 141 .macro fpu_gp_restore reg ctx 142 lw $t0, \reg*4(\ctx) 143 mtc1 $t0,$\reg 144 .endm 145 146 .macro fpu_ct_save reg ctx 147 cfc1 $t0,$1 148 sw $t0, (\reg+32)*4(\ctx) 149 .endm 150 151 .macro fpu_ct_restore reg ctx 152 lw $t0, (\reg+32)*4(\ctx) 153 ctc1 $t0,$\reg 154 .endm 155 156 157 .global fpu_context_save 158 fpu_context_save: 159 #ifdef HAVE_FPU 160 fpu_gp_save 0,$a0 161 fpu_gp_save 1,$a0 162 fpu_gp_save 2,$a0 163 fpu_gp_save 3,$a0 164 fpu_gp_save 4,$a0 165 fpu_gp_save 5,$a0 166 fpu_gp_save 6,$a0 167 fpu_gp_save 7,$a0 168 fpu_gp_save 8,$a0 169 fpu_gp_save 9,$a0 170 fpu_gp_save 10,$a0 171 fpu_gp_save 11,$a0 172 fpu_gp_save 12,$a0 173 fpu_gp_save 13,$a0 174 fpu_gp_save 14,$a0 175 fpu_gp_save 15,$a0 176 fpu_gp_save 16,$a0 177 fpu_gp_save 17,$a0 178 fpu_gp_save 18,$a0 179 fpu_gp_save 19,$a0 180 fpu_gp_save 20,$a0 181 fpu_gp_save 21,$a0 182 fpu_gp_save 22,$a0 183 fpu_gp_save 23,$a0 184 fpu_gp_save 24,$a0 185 fpu_gp_save 25,$a0 186 fpu_gp_save 26,$a0 187 fpu_gp_save 27,$a0 188 fpu_gp_save 28,$a0 189 fpu_gp_save 29,$a0 190 fpu_gp_save 30,$a0 191 fpu_gp_save 31,$a0 192 193 fpu_ct_save 1,$a0 194 fpu_ct_save 2,$a0 195 fpu_ct_save 3,$a0 196 fpu_ct_save 4,$a0 197 fpu_ct_save 5,$a0 198 fpu_ct_save 6,$a0 199 fpu_ct_save 7,$a0 200 fpu_ct_save 8,$a0 201 fpu_ct_save 9,$a0 202 fpu_ct_save 10,$a0 203 fpu_ct_save 11,$a0 204 fpu_ct_save 12,$a0 205 fpu_ct_save 13,$a0 206 fpu_ct_save 14,$a0 207 fpu_ct_save 15,$a0 208 fpu_ct_save 16,$a0 209 fpu_ct_save 17,$a0 210 fpu_ct_save 18,$a0 211 fpu_ct_save 19,$a0 212 fpu_ct_save 20,$a0 213 fpu_ct_save 21,$a0 214 fpu_ct_save 22,$a0 215 fpu_ct_save 23,$a0 216 fpu_ct_save 24,$a0 217 fpu_ct_save 25,$a0 218 fpu_ct_save 26,$a0 219 fpu_ct_save 27,$a0 220 fpu_ct_save 28,$a0 221 fpu_ct_save 29,$a0 222 fpu_ct_save 30,$a0 223 fpu_ct_save 31,$a0 224 #endif 225 j $ra 226 nop 227 228 .global fpu_context_restore 229 fpu_context_restore: 230 #ifdef HAVE_FPU 231 fpu_gp_restore 0,$a0 232 fpu_gp_restore 1,$a0 233 fpu_gp_restore 2,$a0 234 fpu_gp_restore 3,$a0 235 fpu_gp_restore 4,$a0 236 fpu_gp_restore 5,$a0 237 fpu_gp_restore 6,$a0 238 fpu_gp_restore 7,$a0 239 fpu_gp_restore 8,$a0 240 fpu_gp_restore 9,$a0 241 fpu_gp_restore 10,$a0 242 fpu_gp_restore 11,$a0 243 fpu_gp_restore 12,$a0 244 fpu_gp_restore 13,$a0 245 fpu_gp_restore 14,$a0 246 fpu_gp_restore 15,$a0 247 fpu_gp_restore 16,$a0 248 fpu_gp_restore 17,$a0 249 fpu_gp_restore 18,$a0 250 fpu_gp_restore 19,$a0 251 fpu_gp_restore 20,$a0 252 fpu_gp_restore 21,$a0 253 fpu_gp_restore 22,$a0 254 fpu_gp_restore 23,$a0 255 fpu_gp_restore 24,$a0 256 fpu_gp_restore 25,$a0 257 fpu_gp_restore 26,$a0 258 fpu_gp_restore 27,$a0 259 fpu_gp_restore 28,$a0 260 fpu_gp_restore 29,$a0 261 fpu_gp_restore 30,$a0 262 fpu_gp_restore 31,$a0 263 264 fpu_ct_restore 1,$a0 265 fpu_ct_restore 2,$a0 266 fpu_ct_restore 3,$a0 267 fpu_ct_restore 4,$a0 268 fpu_ct_restore 5,$a0 269 fpu_ct_restore 6,$a0 270 fpu_ct_restore 7,$a0 271 fpu_ct_restore 8,$a0 272 fpu_ct_restore 9,$a0 273 fpu_ct_restore 10,$a0 274 fpu_ct_restore 11,$a0 275 fpu_ct_restore 12,$a0 276 fpu_ct_restore 13,$a0 277 fpu_ct_restore 14,$a0 278 fpu_ct_restore 15,$a0 279 fpu_ct_restore 16,$a0 280 fpu_ct_restore 17,$a0 281 fpu_ct_restore 18,$a0 282 fpu_ct_restore 19,$a0 283 fpu_ct_restore 20,$a0 284 fpu_ct_restore 21,$a0 285 fpu_ct_restore 22,$a0 286 fpu_ct_restore 23,$a0 287 fpu_ct_restore 24,$a0 288 fpu_ct_restore 25,$a0 289 fpu_ct_restore 26,$a0 290 fpu_ct_restore 27,$a0 291 fpu_ct_restore 28,$a0 292 fpu_ct_restore 29,$a0 293 fpu_ct_restore 30,$a0 294 fpu_ct_restore 31,$a0 295 #endif 296 j $ra 297 nop 298 158 299 # THIS IS USERSPACE CODE 159 300 .global utext -
arch/mips/src/console.c
rb02e5d1 rffc277e 32 32 #include <arch/console.h> 33 33 34 static void (*putchar_func)(const char ch) = NULL;35 36 34 static void cons_putchar(const char ch) 37 35 { … … 53 51 } 54 52 53 static void (*putchar_func)(const char ch) = cons_putchar; 54 55 55 void console_init(void) 56 56 { -
arch/mips/src/dummy.S
rb02e5d1 rffc277e 33 33 .global asm_delay_loop 34 34 .global dummy 35 .global fpu_enable36 .global fpu_disable37 .global fpu_init38 35 39 36 calibrate_delay_loop: 40 37 asm_delay_loop: 41 fpu_enable:42 fpu_disable:43 fpu_init:44 38 45 39 dummy: -
arch/mips/src/exception.c
rb02e5d1 rffc277e 52 52 cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | 53 53 cp0_status_um_bit)); 54 /* Save pstate so that the threads can access it */ 55 if (THREAD) 56 THREAD->pstate = pstate; 54 57 55 58 /* decode exception number and process the exception */ … … 86 89 break; 87 90 case EXC_CpU: 91 #ifdef FPU_LAZY 92 scheduler_fpu_lazy_request(); 93 #else 88 94 panic("unhandled Coprocessor Unusable Exception\n"); 95 #endif 89 96 break; 90 97 case EXC_Ov: … … 111 118 112 119 pstate->epc += epc_shift; 120 /* Probable not needed, but just for sure that nobody 121 * will continue accessing it */ 122 if (THREAD) 123 THREAD->pstate = NULL; 113 124 } -
arch/mips/src/fpu_context.c
rb02e5d1 rffc277e 29 29 30 30 #include <fpu_context.h> 31 #include <arch.h> 32 #include <arch/cp0.h> 31 33 32 void fpu_context_save(fpu_context_t *fctx) 33 { 34 void fpu_disable(void) 35 { 36 #ifdef HAVE_FPU 37 cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit); 38 if (THREAD && THREAD->pstate) 39 THREAD->pstate->status &= ~cp0_status_fpu_bit; 40 #endif 34 41 } 35 42 36 37 void fpu_context_restore(fpu_context_t *fctx) 43 void fpu_enable(void) 38 44 { 45 #ifdef HAVE_FPU 46 cp0_status_write(cp0_status_read() | cp0_status_fpu_bit); 47 if (THREAD && THREAD->pstate) 48 THREAD->pstate->status |= cp0_status_fpu_bit; 49 #endif 39 50 } 40 51 52 void fpu_init(void) 53 { 54 /* TODO: Zero all registers */ 55 } -
arch/mips/src/mips.c
rb02e5d1 rffc277e 35 35 #include <userspace.h> 36 36 #include <arch/console.h> 37 #include <memstr.h> 38 39 /* Size of the code jumping to the exception handler code 40 * - J+NOP 41 */ 42 #define EXCEPTION_JUMP_SIZE 8 43 44 #define TLB_EXC ((char *) 0x80000000) 45 #define NORM_EXC ((char *) 0x80000180) 46 #define CACHE_EXC ((char *) 0x80000100) 47 48 #include <arch/debug.h> 37 49 38 50 void arch_pre_mm_init(void) 39 51 { 52 /* Copy the exception vectors to the right places */ 53 memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); 54 memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); 55 memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); 56 57 40 58 /* 41 59 * Switch to BEV normal level so that exception vectors point to the kernel. -
arch/mips/src/mm/frame.c
rb02e5d1 rffc277e 32 32 void frame_arch_init(void) 33 33 { 34 /* Disable first megabyte (God knows why) */ 35 frame_region_not_free(0, 1024*1024); 34 36 } -
arch/mips/src/panic.S
rb02e5d1 rffc277e 33 33 .set nomacro 34 34 35 #include <arch/asm/regname.h> 36 35 37 .global panic_printf 36 38 39 /* From printf return directly to halt() */ 37 40 panic_printf: 38 jal printf 39 nop 40 j cpu_halt 41 nop 42 41 lui $ra, %hi(halt) 42 j printf 43 ori $ra, %lo(halt) -
arch/mips/src/start.S
rb02e5d1 rffc277e 154 154 155 155 .org 0x0 156 tlb_refill_entry:157 j tlb_refill_handler158 nop159 160 .org 0x100161 cache_error_entry:162 j cache_error_handler163 nop164 165 .org 0x180166 norm_exception:167 j exception_handler168 nop169 170 .org 0x200171 iv_exception:172 j exception_handler173 nop174 175 .org KA2PA(KERNEL_STARTUP_ADDRESS)176 156 kernel_image_start: 177 157 /* Load temporary stack */ … … 187 167 188 168 .space TEMP_STACK_SIZE 189 end_stack: 169 end_stack: 170 171 tlb_refill_entry: 172 j tlb_refill_handler 173 nop 174 175 cache_error_entry: 176 j cache_error_handler 177 nop 178 179 exception_entry: 180 j exception_handler 181 nop 182 183 190 184 191 185 exception_handler: 192 exception_entry:193 186 KERNEL_STACK_TO_K0 194 187 sub $k0, REGISTER_SPACE
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