source: mainline/arch/mips/src/asm.S@ ffc277e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ffc277e was ffc277e, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Cleanup of makefiles to have common options in one main makefile.

Add simple build process for different simulators for MIPS.
Added FPU context & lazy FPU context switching to MIPS.
Cleanup of MIPS linker script.
Moved MIPS kernel above 1MB. Not tested on real machine yet, but it might help.

There is something broken with gcc inlined memcpy (either simulator or gcc), it is disabled on BigEndian mips now.

  • Property mode set to 100644
File size: 6.4 KB
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1#
2# Copyright (C) 2003-2004 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/asm/regname.h>
30
31.text
32
33.macro cp0_read reg
34 mfc0 $2,\reg
35 j $31
36 nop
37.endm
38
39.macro cp0_write reg
40 mtc0 $4,\reg
41 j $31
42 nop
43.endm
44
45.set noat
46.set noreorder
47.set nomacro
48
49.global cp0_index_read
50.global cp0_index_write
51.global cp0_random_read
52.global cp0_entry_lo0_read
53.global cp0_entry_lo0_write
54.global cp0_entry_lo1_read
55.global cp0_entry_lo1_write
56.global cp0_context_read
57.global cp0_context_write
58.global cp0_pagemask_read
59.global cp0_pagemask_write
60.global cp0_wired_read
61.global cp0_wired_write
62.global cp0_badvaddr_read
63.global cp0_count_read
64.global cp0_count_write
65.global cp0_hi_read
66.global cp0_hi_write
67.global cp0_compare_read
68.global cp0_compare_write
69.global cp0_status_read
70.global cp0_status_write
71.global cp0_cause_read
72.global cp0_cause_write
73.global cp0_epc_read
74.global cp0_epc_write
75.global cp0_prid_read
76
77cp0_index_read: cp0_read $0
78cp0_index_write: cp0_write $0
79
80cp0_random_read: cp0_read $1
81
82cp0_entry_lo0_read: cp0_read $2
83cp0_entry_lo0_write: cp0_write $2
84
85cp0_entry_lo1_read: cp0_read $3
86cp0_entry_lo1_write: cp0_write $3
87
88cp0_context_read: cp0_read $4
89cp0_context_write: cp0_write $4
90
91cp0_pagemask_read: cp0_read $5
92cp0_pagemask_write: cp0_write $5
93
94cp0_wired_read: cp0_read $6
95cp0_wired_write: cp0_write $6
96
97cp0_badvaddr_read: cp0_read $8
98
99cp0_count_read: cp0_read $9
100cp0_count_write: cp0_write $9
101
102cp0_entry_hi_read: cp0_read $10
103cp0_entry_hi_write: cp0_write $10
104
105cp0_compare_read: cp0_read $11
106cp0_compare_write: cp0_write $11
107
108cp0_status_read: cp0_read $12
109cp0_status_write: cp0_write $12
110
111cp0_cause_read: cp0_read $13
112cp0_cause_write: cp0_write $13
113
114cp0_epc_read: cp0_read $14
115cp0_epc_write: cp0_write $14
116
117cp0_prid_read: cp0_read $15
118
119
120.global cpu_halt
121cpu_halt:
122 j cpu_halt
123 nop
124
125
126.global memsetb
127memsetb:
128 j _memsetb
129 nop
130
131.global memcpy
132memcpy:
133 j _memcpy
134 nop
135
136.macro fpu_gp_save reg ctx
137 mfc1 $t0,$\reg
138 sw $t0, \reg*4(\ctx)
139.endm
140
141.macro fpu_gp_restore reg ctx
142 lw $t0, \reg*4(\ctx)
143 mtc1 $t0,$\reg
144.endm
145
146.macro fpu_ct_save reg ctx
147 cfc1 $t0,$1
148 sw $t0, (\reg+32)*4(\ctx)
149.endm
150
151.macro fpu_ct_restore reg ctx
152 lw $t0, (\reg+32)*4(\ctx)
153 ctc1 $t0,$\reg
154.endm
155
156
157.global fpu_context_save
158fpu_context_save:
159#ifdef HAVE_FPU
160 fpu_gp_save 0,$a0
161 fpu_gp_save 1,$a0
162 fpu_gp_save 2,$a0
163 fpu_gp_save 3,$a0
164 fpu_gp_save 4,$a0
165 fpu_gp_save 5,$a0
166 fpu_gp_save 6,$a0
167 fpu_gp_save 7,$a0
168 fpu_gp_save 8,$a0
169 fpu_gp_save 9,$a0
170 fpu_gp_save 10,$a0
171 fpu_gp_save 11,$a0
172 fpu_gp_save 12,$a0
173 fpu_gp_save 13,$a0
174 fpu_gp_save 14,$a0
175 fpu_gp_save 15,$a0
176 fpu_gp_save 16,$a0
177 fpu_gp_save 17,$a0
178 fpu_gp_save 18,$a0
179 fpu_gp_save 19,$a0
180 fpu_gp_save 20,$a0
181 fpu_gp_save 21,$a0
182 fpu_gp_save 22,$a0
183 fpu_gp_save 23,$a0
184 fpu_gp_save 24,$a0
185 fpu_gp_save 25,$a0
186 fpu_gp_save 26,$a0
187 fpu_gp_save 27,$a0
188 fpu_gp_save 28,$a0
189 fpu_gp_save 29,$a0
190 fpu_gp_save 30,$a0
191 fpu_gp_save 31,$a0
192
193 fpu_ct_save 1,$a0
194 fpu_ct_save 2,$a0
195 fpu_ct_save 3,$a0
196 fpu_ct_save 4,$a0
197 fpu_ct_save 5,$a0
198 fpu_ct_save 6,$a0
199 fpu_ct_save 7,$a0
200 fpu_ct_save 8,$a0
201 fpu_ct_save 9,$a0
202 fpu_ct_save 10,$a0
203 fpu_ct_save 11,$a0
204 fpu_ct_save 12,$a0
205 fpu_ct_save 13,$a0
206 fpu_ct_save 14,$a0
207 fpu_ct_save 15,$a0
208 fpu_ct_save 16,$a0
209 fpu_ct_save 17,$a0
210 fpu_ct_save 18,$a0
211 fpu_ct_save 19,$a0
212 fpu_ct_save 20,$a0
213 fpu_ct_save 21,$a0
214 fpu_ct_save 22,$a0
215 fpu_ct_save 23,$a0
216 fpu_ct_save 24,$a0
217 fpu_ct_save 25,$a0
218 fpu_ct_save 26,$a0
219 fpu_ct_save 27,$a0
220 fpu_ct_save 28,$a0
221 fpu_ct_save 29,$a0
222 fpu_ct_save 30,$a0
223 fpu_ct_save 31,$a0
224#endif
225 j $ra
226 nop
227
228.global fpu_context_restore
229fpu_context_restore:
230#ifdef HAVE_FPU
231 fpu_gp_restore 0,$a0
232 fpu_gp_restore 1,$a0
233 fpu_gp_restore 2,$a0
234 fpu_gp_restore 3,$a0
235 fpu_gp_restore 4,$a0
236 fpu_gp_restore 5,$a0
237 fpu_gp_restore 6,$a0
238 fpu_gp_restore 7,$a0
239 fpu_gp_restore 8,$a0
240 fpu_gp_restore 9,$a0
241 fpu_gp_restore 10,$a0
242 fpu_gp_restore 11,$a0
243 fpu_gp_restore 12,$a0
244 fpu_gp_restore 13,$a0
245 fpu_gp_restore 14,$a0
246 fpu_gp_restore 15,$a0
247 fpu_gp_restore 16,$a0
248 fpu_gp_restore 17,$a0
249 fpu_gp_restore 18,$a0
250 fpu_gp_restore 19,$a0
251 fpu_gp_restore 20,$a0
252 fpu_gp_restore 21,$a0
253 fpu_gp_restore 22,$a0
254 fpu_gp_restore 23,$a0
255 fpu_gp_restore 24,$a0
256 fpu_gp_restore 25,$a0
257 fpu_gp_restore 26,$a0
258 fpu_gp_restore 27,$a0
259 fpu_gp_restore 28,$a0
260 fpu_gp_restore 29,$a0
261 fpu_gp_restore 30,$a0
262 fpu_gp_restore 31,$a0
263
264 fpu_ct_restore 1,$a0
265 fpu_ct_restore 2,$a0
266 fpu_ct_restore 3,$a0
267 fpu_ct_restore 4,$a0
268 fpu_ct_restore 5,$a0
269 fpu_ct_restore 6,$a0
270 fpu_ct_restore 7,$a0
271 fpu_ct_restore 8,$a0
272 fpu_ct_restore 9,$a0
273 fpu_ct_restore 10,$a0
274 fpu_ct_restore 11,$a0
275 fpu_ct_restore 12,$a0
276 fpu_ct_restore 13,$a0
277 fpu_ct_restore 14,$a0
278 fpu_ct_restore 15,$a0
279 fpu_ct_restore 16,$a0
280 fpu_ct_restore 17,$a0
281 fpu_ct_restore 18,$a0
282 fpu_ct_restore 19,$a0
283 fpu_ct_restore 20,$a0
284 fpu_ct_restore 21,$a0
285 fpu_ct_restore 22,$a0
286 fpu_ct_restore 23,$a0
287 fpu_ct_restore 24,$a0
288 fpu_ct_restore 25,$a0
289 fpu_ct_restore 26,$a0
290 fpu_ct_restore 27,$a0
291 fpu_ct_restore 28,$a0
292 fpu_ct_restore 29,$a0
293 fpu_ct_restore 30,$a0
294 fpu_ct_restore 31,$a0
295#endif
296 j $ra
297 nop
298
299# THIS IS USERSPACE CODE
300.global utext
301utext:
302 j $31
303 nop
304utext_end:
305
306.data
307.global utext_size
308utext_size:
309 .long utext_end-utext
310
311
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