source: mainline/arch/mips/src/exception.c@ 178ec7b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 178ec7b was 178ec7b, checked in by Jakub Jermar <jakub@…>, 20 years ago

Copyright notices changes.
  • Property mode set to 100644
File size: 3.6 KB
Line 
1/*
2 * Copyright (C) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/exception.h>
30#include <arch/interrupt.h>
31#include <panic.h>
32#include <arch/cp0.h>
33#include <arch/types.h>
34#include <arch.h>
35#include <debug.h>
36
37void exception(struct exception_regdump *pstate)
38{
39 int excno;
40 __u32 epc_shift = 0;
41
42 ASSERT(CPU != NULL);
43
44 /*
45 * NOTE ON OPERATION ORDERING
46 *
47 * On entry, cpu_priority_high() must be called before
48 * exception bit is cleared.
49 */
50
51 cpu_priority_high();
52 cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
53 cp0_status_um_bit));
54
55 /* decode exception number and process the exception */
56 switch (excno = (cp0_cause_read() >> 2) & 0x1f) {
57 case EXC_Int:
58 interrupt();
59 break;
60 case EXC_TLBL:
61 case EXC_TLBS:
62 tlb_invalid(pstate);
63 break;
64 case EXC_Mod:
65 panic("unhandled TLB Modification Exception\n");
66 break;
67 case EXC_AdEL:
68 panic("unhandled Address Error Exception - load or instruction fetch\n");
69 break;
70 case EXC_AdES:
71 panic("unhandled Address Error Exception - store\n");
72 break;
73 case EXC_IBE:
74 panic("unhandled Bus Error Exception - fetch instruction\n");
75 break;
76 case EXC_DBE:
77 panic("unhandled Bus Error Exception - data reference: load or store\n");
78 break;
79 case EXC_Bp:
80 /* it is necessary to not re-execute BREAK instruction after returning from Exception handler
81 (see page 138 in R4000 Manual for more information) */
82 epc_shift = 4;
83 break;
84 case EXC_RI:
85 panic("unhandled Reserved Instruction Exception\n");
86 break;
87 case EXC_CpU:
88 panic("unhandled Coprocessor Unusable Exception\n");
89 break;
90 case EXC_Ov:
91 panic("unhandled Arithmetic Overflow Exception\n");
92 break;
93 case EXC_Tr:
94 panic("unhandled Trap Exception\n");
95 break;
96 case EXC_VCEI:
97 panic("unhandled Virtual Coherency Exception - instruction\n");
98 break;
99 case EXC_FPE:
100 panic("unhandled Floating-Point Exception\n");
101 break;
102 case EXC_WATCH:
103 panic("unhandled reference to WatchHi/WatchLo address\n");
104 break;
105 case EXC_VCED:
106 panic("unhandled Virtual Coherency Exception - data\n");
107 break;
108 default:
109 panic("unhandled exception %d\n", excno);
110 }
111
112 pstate->epc += epc_shift;
113}
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