Changeset ffc277e in mainline for arch/mips/src/asm.S

Timestamp:

2005-09-10T00:52:13Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f3a6c8e5

Parents:

b02e5d1

Message:

Cleanup of makefiles to have common options in one main makefile.

Add simple build process for different simulators for MIPS.
Added FPU context & lazy FPU context switching to MIPS.
Cleanup of MIPS linker script.
Moved MIPS kernel above 1MB. Not tested on real machine yet, but it might help.

There is something broken with gcc inlined memcpy (either simulator or gcc), it is disabled on BigEndian mips now.

File:

• arch/mips/src/asm.S (modified) (3 diffs)

arch/mips/src/asm.S

@@ -27 +27 @@
 #
 
+#include <arch/asm/regname.h>
+        
 .text
 
@@ -116 +118 @@
 
 
-.global tlbp
-tlbp:
-        tlbp
-        j $31
-        nop
-
-.global tlbr
-tlbr:
-        tlbr
-        j $31
-        nop
-
-.global tlbwi
-tlbwi:
-        tlbwi
-        j $31
-        nop
-
-.global tlbwr
-tlbwr:
-        tlbwr
-        j $31
-        nop
-
 .global cpu_halt
 cpu_halt:
@@ -156 +134 @@
         nop
 
+.macro fpu_gp_save reg ctx
+        mfc1 $t0,$\reg
+        sw $t0, \reg*4(\ctx)
+.endm
+
+.macro fpu_gp_restore reg ctx
+        lw $t0, \reg*4(\ctx)
+        mtc1 $t0,$\reg
+.endm
+
+.macro fpu_ct_save reg ctx
+        cfc1 $t0,$1
+        sw $t0, (\reg+32)*4(\ctx)
+.endm   
+
+.macro fpu_ct_restore reg ctx
+        lw $t0, (\reg+32)*4(\ctx)
+        ctc1 $t0,$\reg
+.endm
+
+
+.global fpu_context_save
+fpu_context_save:
+#ifdef HAVE_FPU
+        fpu_gp_save 0,$a0
+        fpu_gp_save 1,$a0
+        fpu_gp_save 2,$a0
+        fpu_gp_save 3,$a0
+        fpu_gp_save 4,$a0
+        fpu_gp_save 5,$a0
+        fpu_gp_save 6,$a0
+        fpu_gp_save 7,$a0
+        fpu_gp_save 8,$a0
+        fpu_gp_save 9,$a0
+        fpu_gp_save 10,$a0
+        fpu_gp_save 11,$a0
+        fpu_gp_save 12,$a0
+        fpu_gp_save 13,$a0
+        fpu_gp_save 14,$a0
+        fpu_gp_save 15,$a0
+        fpu_gp_save 16,$a0
+        fpu_gp_save 17,$a0
+        fpu_gp_save 18,$a0
+        fpu_gp_save 19,$a0
+        fpu_gp_save 20,$a0
+        fpu_gp_save 21,$a0
+        fpu_gp_save 22,$a0
+        fpu_gp_save 23,$a0
+        fpu_gp_save 24,$a0
+        fpu_gp_save 25,$a0
+        fpu_gp_save 26,$a0
+        fpu_gp_save 27,$a0
+        fpu_gp_save 28,$a0
+        fpu_gp_save 29,$a0
+        fpu_gp_save 30,$a0
+        fpu_gp_save 31,$a0
+
+        fpu_ct_save 1,$a0
+        fpu_ct_save 2,$a0
+        fpu_ct_save 3,$a0
+        fpu_ct_save 4,$a0
+        fpu_ct_save 5,$a0
+        fpu_ct_save 6,$a0
+        fpu_ct_save 7,$a0
+        fpu_ct_save 8,$a0
+        fpu_ct_save 9,$a0
+        fpu_ct_save 10,$a0
+        fpu_ct_save 11,$a0
+        fpu_ct_save 12,$a0
+        fpu_ct_save 13,$a0
+        fpu_ct_save 14,$a0
+        fpu_ct_save 15,$a0
+        fpu_ct_save 16,$a0
+        fpu_ct_save 17,$a0
+        fpu_ct_save 18,$a0
+        fpu_ct_save 19,$a0
+        fpu_ct_save 20,$a0
+        fpu_ct_save 21,$a0
+        fpu_ct_save 22,$a0
+        fpu_ct_save 23,$a0
+        fpu_ct_save 24,$a0
+        fpu_ct_save 25,$a0
+        fpu_ct_save 26,$a0
+        fpu_ct_save 27,$a0
+        fpu_ct_save 28,$a0
+        fpu_ct_save 29,$a0
+        fpu_ct_save 30,$a0
+        fpu_ct_save 31,$a0
+#endif          
+        j $ra
+        nop
+
+.global fpu_context_restore
+fpu_context_restore:
+#ifdef HAVE_FPU
+        fpu_gp_restore 0,$a0
+        fpu_gp_restore 1,$a0
+        fpu_gp_restore 2,$a0
+        fpu_gp_restore 3,$a0
+        fpu_gp_restore 4,$a0
+        fpu_gp_restore 5,$a0
+        fpu_gp_restore 6,$a0
+        fpu_gp_restore 7,$a0
+        fpu_gp_restore 8,$a0
+        fpu_gp_restore 9,$a0
+        fpu_gp_restore 10,$a0
+        fpu_gp_restore 11,$a0
+        fpu_gp_restore 12,$a0
+        fpu_gp_restore 13,$a0
+        fpu_gp_restore 14,$a0
+        fpu_gp_restore 15,$a0
+        fpu_gp_restore 16,$a0
+        fpu_gp_restore 17,$a0
+        fpu_gp_restore 18,$a0
+        fpu_gp_restore 19,$a0
+        fpu_gp_restore 20,$a0
+        fpu_gp_restore 21,$a0
+        fpu_gp_restore 22,$a0
+        fpu_gp_restore 23,$a0
+        fpu_gp_restore 24,$a0
+        fpu_gp_restore 25,$a0
+        fpu_gp_restore 26,$a0
+        fpu_gp_restore 27,$a0
+        fpu_gp_restore 28,$a0
+        fpu_gp_restore 29,$a0
+        fpu_gp_restore 30,$a0
+        fpu_gp_restore 31,$a0
+
+        fpu_ct_restore 1,$a0
+        fpu_ct_restore 2,$a0
+        fpu_ct_restore 3,$a0
+        fpu_ct_restore 4,$a0
+        fpu_ct_restore 5,$a0
+        fpu_ct_restore 6,$a0
+        fpu_ct_restore 7,$a0
+        fpu_ct_restore 8,$a0
+        fpu_ct_restore 9,$a0
+        fpu_ct_restore 10,$a0
+        fpu_ct_restore 11,$a0
+        fpu_ct_restore 12,$a0
+        fpu_ct_restore 13,$a0
+        fpu_ct_restore 14,$a0
+        fpu_ct_restore 15,$a0
+        fpu_ct_restore 16,$a0
+        fpu_ct_restore 17,$a0
+        fpu_ct_restore 18,$a0
+        fpu_ct_restore 19,$a0
+        fpu_ct_restore 20,$a0
+        fpu_ct_restore 21,$a0
+        fpu_ct_restore 22,$a0
+        fpu_ct_restore 23,$a0
+        fpu_ct_restore 24,$a0
+        fpu_ct_restore 25,$a0
+        fpu_ct_restore 26,$a0
+        fpu_ct_restore 27,$a0
+        fpu_ct_restore 28,$a0
+        fpu_ct_restore 29,$a0
+        fpu_ct_restore 30,$a0
+        fpu_ct_restore 31,$a0
+#endif  
+        j $ra
+        nop
+        
 # THIS IS USERSPACE CODE
 .global utext