Changeset 3bacee1 in mainline for kernel/arch

Timestamp:

2018-04-12T16:27:17Z (7 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

3cf22f9

Parents:

76d0981d

git-author:

Jiri Svoboda <jiri@…> (2018-04-11 19:25:33)

git-committer:

Jiri Svoboda <jiri@…> (2018-04-12 16:27:17)

Message:

Make ccheck-fix again and commit more good files.

Location:

kernel/arch

Files:

• amd64/include/arch/asm.h (modified) (18 diffs)
• amd64/src/amd64.c (modified) (1 diff)
• arm32/include/arch/asm.h (modified) (2 diffs)
• arm32/include/arch/security_ext.h (modified) (1 diff)
• arm32/src/mach/raspberrypi/raspberrypi.c (modified) (4 diffs)
• arm32/src/mm/page.c (modified) (1 diff)
• ia32/include/arch/asm.h (modified) (19 diffs)
• ia32/src/cpu/cpu.c (modified) (4 diffs)
• ia32/src/ia32.c (modified) (1 diff)
• ia64/src/drivers/ski.c (modified) (3 diffs)
• ia64/src/ia64.c (modified) (3 diffs)
• ia64/src/interrupt.c (modified) (2 diffs)
• mips32/include/arch/asm.h (modified) (1 diff)
• mips32/include/arch/mm/tlb.h (modified) (4 diffs)
• mips32/src/debugger.c (modified) (4 diffs)
• mips32/src/mach/msim/msim.c (modified) (1 diff)
• mips32/src/mm/km.c (modified) (1 diff)
• ppc32/src/mm/pht.c (modified) (2 diffs)
• ppc32/src/ppc32.c (modified) (3 diffs)
• sparc64/include/arch/asm.h (modified) (26 diffs)
• sparc64/src/fpu_context.c (modified) (4 diffs)
• sparc64/src/sun4v/md.c (modified) (5 diffs)

kernel/arch/amd64/include/arch/asm.h

@@ -55 +55 @@
 
         asm volatile (
-                "andq %%rsp, %[v]\n"
-                : [v] "=r" (v)
-                : "0" (~((uint64_t) STACK_SIZE - 1))
+            "andq %%rsp, %[v]\n"
+            : [v] "=r" (v)
+            : "0" (~((uint64_t) STACK_SIZE - 1))
         );
 
@@ -66 +66 @@
 {
         asm volatile (
-                "hlt\n"
+            "hlt\n"
         );
 }
@@ -74 +74 @@
         while (true) {
                 asm volatile (
-                        "hlt\n"
+                    "hlt\n"
                 );
         }
@@ -93 +93 @@
 
                 asm volatile (
-                        "inb %w[port], %b[val]\n"
-                        : [val] "=a" (val)
-                        : [port] "d" (port)
+                    "inb %w[port], %b[val]\n"
+                    : [val] "=a" (val)
+                    : [port] "d" (port)
                 );
 
@@ -117 +117 @@
 
                 asm volatile (
-                        "inw %w[port], %w[val]\n"
-                        : [val] "=a" (val)
-                        : [port] "d" (port)
+                    "inw %w[port], %w[val]\n"
+                    : [val] "=a" (val)
+                    : [port] "d" (port)
                 );
 
@@ -141 +141 @@
 
                 asm volatile (
-                        "inl %w[port], %[val]\n"
-                        : [val] "=a" (val)
-                        : [port] "d" (port)
+                    "inl %w[port], %[val]\n"
+                    : [val] "=a" (val)
+                    : [port] "d" (port)
                 );
 
@@ -163 +163 @@
         if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
                 asm volatile (
-                        "outb %b[val], %w[port]\n"
-                        :: [val] "a" (val), [port] "d" (port)
+                    "outb %b[val], %w[port]\n"
+                    :: [val] "a" (val), [port] "d" (port)
                 );
         } else
@@ -182 +182 @@
         if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
                 asm volatile (
-                        "outw %w[val], %w[port]\n"
-                        :: [val] "a" (val), [port] "d" (port)
+                    "outw %w[val], %w[port]\n"
+                    :: [val] "a" (val), [port] "d" (port)
                 );
         } else
@@ -201 +201 @@
         if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
                 asm volatile (
-                        "outl %[val], %w[port]\n"
-                        :: [val] "a" (val), [port] "d" (port)
+                    "outl %[val], %w[port]\n"
+                    :: [val] "a" (val), [port] "d" (port)
                 );
         } else
@@ -213 +213 @@
 
         asm volatile (
-                "pushfq\n"
-                "popq %[v]\n"
-                : [v] "=r" (rflags)
+            "pushfq\n"
+            "popq %[v]\n"
+            : [v] "=r" (rflags)
         );
 
@@ -224 +224 @@
 {
         asm volatile (
-                "pushq %[v]\n"
-                "popfq\n"
-                :: [v] "r" (rflags)
+            "pushq %[v]\n"
+            "popfq\n"
+            :: [v] "r" (rflags)
         );
 }
@@ -300 +300 @@
 {
         asm volatile (
-                "wrmsr\n"
-                :: "c" (msr),
-                   "a" ((uint32_t) (value)),
-                   "d" ((uint32_t) (value >> 32))
+            "wrmsr\n"
+            :: "c" (msr),
+              "a" ((uint32_t) (value)),
+              "d" ((uint32_t) (value >> 32))
         );
 }
@@ -312 +312 @@
 
         asm volatile (
-                "rdmsr\n"
-                : "=a" (ax), "=d" (dx)
-                : "c" (msr)
+            "rdmsr\n"
+            : "=a" (ax), "=d" (dx)
+            : "c" (msr)
         );
 
@@ -328 +328 @@
 {
         asm volatile (
-                "invlpg %[addr]\n"
-                :: [addr] "m" (*((sysarg_t *) addr))
+            "invlpg %[addr]\n"
+            :: [addr] "m" (*((sysarg_t *) addr))
         );
 }
@@ -341 +341 @@
 {
         asm volatile (
-                "lgdtq %[gdtr_reg]\n"
-                :: [gdtr_reg] "m" (*gdtr_reg)
+            "lgdtq %[gdtr_reg]\n"
+            :: [gdtr_reg] "m" (*gdtr_reg)
         );
 }
@@ -354 +354 @@
 {
         asm volatile (
-                "sgdtq %[gdtr_reg]\n"
-                :: [gdtr_reg] "m" (*gdtr_reg)
+            "sgdtq %[gdtr_reg]\n"
+            :: [gdtr_reg] "m" (*gdtr_reg)
         );
 }
@@ -367 +367 @@
 {
         asm volatile (
-                "lidtq %[idtr_reg]\n"
-                :: [idtr_reg] "m" (*idtr_reg));
+            "lidtq %[idtr_reg]\n"
+            :: [idtr_reg] "m" (*idtr_reg));
 }
 
@@ -379 +379 @@
 {
         asm volatile (
-                "ltr %[sel]"
-                :: [sel] "r" (sel)
+            "ltr %[sel]"
+            :: [sel] "r" (sel)
         );
 }

kernel/arch/amd64/src/amd64.c

@@ -215 +215 @@
         outdev_t **ns16550_out_ptr = NULL;
 #endif
-        ns16550_instance_t *ns16550_instance
-            = ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
+        ns16550_instance_t *ns16550_instance =
+            ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
             ns16550_out_ptr);
         if (ns16550_instance) {

kernel/arch/arm32/include/arch/asm.h

@@ -59 +59 @@
 {
 #ifdef PROCESSOR_ARCH_armv7_a
-        asm volatile ( "wfe" );
+        asm volatile ("wfe");
 #elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
         WFI_write(0);
@@ -107 +107 @@
 
         asm volatile (
-                "and %[v], sp, %[size]\n"
-                : [v] "=r" (v)
-                : [size] "r" (~(STACK_SIZE - 1))
+            "and %[v], sp, %[size]\n"
+            : [v] "=r" (v)
+            : [size] "r" (~(STACK_SIZE - 1))
         );
 

kernel/arch/arm32/include/arch/security_ext.h

@@ -77 +77 @@
 static inline bool sec_ext_is_secure(void)
 {
-        return sec_ext_is_implemented()
-            && (sec_ext_is_monitor_mode() || !(SCR_read() & SCR_NS_FLAG));
+        return sec_ext_is_implemented() &&
+            (sec_ext_is_monitor_mode() || !(SCR_read() & SCR_NS_FLAG));
 }
 

kernel/arch/arm32/src/mach/raspberrypi/raspberrypi.c

@@ -103 +103 @@
         /* Initialize interrupt controller */
         raspi.irc = (void *) km_map(BCM2835_IRC_ADDR, sizeof(bcm2835_irc_t),
-                                    PAGE_NOT_CACHEABLE);
+            PAGE_NOT_CACHEABLE);
         assert(raspi.irc);
         bcm2835_irc_init(raspi.irc);
@@ -109 +109 @@
         /* Initialize system timer */
         raspi.timer = (void *) km_map(BCM2835_TIMER_ADDR,
-                                      sizeof(bcm2835_timer_t),
-                                      PAGE_NOT_CACHEABLE);
+            sizeof(bcm2835_timer_t),
+            PAGE_NOT_CACHEABLE);
 }
 
@@ -129 +129 @@
 static void raspberrypi_cpu_halt(void)
 {
-        while (true) ;
+        while (true)
+                ;
 }
 
@@ -184 +185 @@
 #ifdef CONFIG_PL011_UART
         if (pl011_uart_init(&raspi.uart, BCM2835_UART_IRQ,
-                            BCM2835_UART0_BASE_ADDRESS))
+            BCM2835_UART0_BASE_ADDRESS))
                 stdout_wire(&raspi.uart.outdev);
 #endif

kernel/arch/arm32/src/mm/page.c

@@ -63 +63 @@
         for (uintptr_t cur = PHYSMEM_START_ADDR;
             cur < min(KA2PA(config.identity_base) +
-                config.identity_size, config.physmem_end);
+            config.identity_size, config.physmem_end);
             cur += FRAME_SIZE)
                 page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);

kernel/arch/ia32/include/arch/asm.h

@@ -52 +52 @@
         while (true) {
                 asm volatile (
-                        "hlt\n"
+                    "hlt\n"
                 );
         }
@@ -60 +60 @@
 {
         asm volatile (
-                "hlt\n"
+            "hlt\n"
         );
 }
@@ -117 +117 @@
         if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
                 asm volatile (
-                        "outb %b[val], %w[port]\n"
-                        :: [val] "a" (val), [port] "d" (port)
+                    "outb %b[val], %w[port]\n"
+                    :: [val] "a" (val), [port] "d" (port)
                 );
         } else
@@ -136 +136 @@
         if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
                 asm volatile (
-                        "outw %w[val], %w[port]\n"
-                        :: [val] "a" (val), [port] "d" (port)
+                    "outw %w[val], %w[port]\n"
+                    :: [val] "a" (val), [port] "d" (port)
                 );
         } else
@@ -155 +155 @@
         if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
                 asm volatile (
-                        "outl %[val], %w[port]\n"
-                        :: [val] "a" (val), [port] "d" (port)
+                    "outl %[val], %w[port]\n"
+                    :: [val] "a" (val), [port] "d" (port)
                 );
         } else
@@ -176 +176 @@
 
                 asm volatile (
-                        "inb %w[port], %b[val]\n"
-                        : [val] "=a" (val)
-                        : [port] "d" (port)
+                    "inb %w[port], %b[val]\n"
+                    : [val] "=a" (val)
+                    : [port] "d" (port)
                 );
 
@@ -200 +200 @@
 
                 asm volatile (
-                        "inw %w[port], %w[val]\n"
-                        : [val] "=a" (val)
-                        : [port] "d" (port)
+                    "inw %w[port], %w[val]\n"
+                    : [val] "=a" (val)
+                    : [port] "d" (port)
                 );
 
@@ -224 +224 @@
 
                 asm volatile (
-                        "inl %w[port], %[val]\n"
-                        : [val] "=a" (val)
-                        : [port] "d" (port)
+                    "inl %w[port], %[val]\n"
+                    : [val] "=a" (val)
+                    : [port] "d" (port)
                 );
 
@@ -239 +239 @@
 
         asm volatile (
-                "pushf\n"
-                "popl %[v]\n"
-                : [v] "=r" (eflags)
+            "pushf\n"
+            "popl %[v]\n"
+            : [v] "=r" (eflags)
         );
 
@@ -250 +250 @@
 {
         asm volatile (
-                "pushl %[v]\n"
-                "popf\n"
-                :: [v] "r" (eflags)
+            "pushl %[v]\n"
+            "popf\n"
+            :: [v] "r" (eflags)
         );
 }
@@ -326 +326 @@
 {
         asm volatile (
-                "wrmsr"
-                :: "c" (msr),
-                   "a" ((uint32_t) (value)),
-                   "d" ((uint32_t) (value >> 32))
+            "wrmsr"
+            :: "c" (msr),
+              "a" ((uint32_t) (value)),
+              "d" ((uint32_t) (value >> 32))
         );
 }
@@ -338 +338 @@
 
         asm volatile (
-                "rdmsr"
-                : "=a" (ax),
-                  "=d" (dx)
-                : "c" (msr)
+            "rdmsr"
+            : "=a" (ax),
+              "=d" (dx)
+            : "c" (msr)
         );
 
@@ -362 +362 @@
 
         asm volatile (
-                "andl %%esp, %[v]\n"
-                : [v] "=r" (v)
-                : "0" (~(STACK_SIZE - 1))
+            "andl %%esp, %[v]\n"
+            : [v] "=r" (v)
+            : "0" (~(STACK_SIZE - 1))
         );
 
@@ -378 +378 @@
 {
         asm volatile (
-                "invlpg %[addr]\n"
-                :: [addr] "m" (*(sysarg_t *) addr)
+            "invlpg %[addr]\n"
+            :: [addr] "m" (*(sysarg_t *) addr)
         );
 }
@@ -391 +391 @@
 {
         asm volatile (
-                "lgdtl %[gdtr_reg]\n"
-                :: [gdtr_reg] "m" (*gdtr_reg)
+            "lgdtl %[gdtr_reg]\n"
+            :: [gdtr_reg] "m" (*gdtr_reg)
         );
 }
@@ -404 +404 @@
 {
         asm volatile (
-                "sgdtl %[gdtr_reg]\n"
-                : [gdtr_reg] "=m" (*gdtr_reg)
+            "sgdtl %[gdtr_reg]\n"
+            : [gdtr_reg] "=m" (*gdtr_reg)
         );
 }
@@ -417 +417 @@
 {
         asm volatile (
-                "lidtl %[idtr_reg]\n"
-                :: [idtr_reg] "m" (*idtr_reg)
+            "lidtl %[idtr_reg]\n"
+            :: [idtr_reg] "m" (*idtr_reg)
         );
 }
@@ -430 +430 @@
 {
         asm volatile (
-                "ltr %[sel]"
-                :: [sel] "r" (sel)
+            "ltr %[sel]"
+            :: [sel] "r" (sel)
         );
 }
@@ -443 +443 @@
 {
         asm volatile (
-                "mov %[sel], %%gs"
-                :: [sel] "r" (sel)
+            "mov %[sel], %%gs"
+            :: [sel] "r" (sel)
         );
 }

kernel/arch/ia32/src/cpu/cpu.c

@@ -101 +101 @@
         if (CPU->arch.fi.bits.sse) {
                 asm volatile (
-                        "mov %%cr4, %[help]\n"
-                        "or %[mask], %[help]\n"
-                        "mov %[help], %%cr4\n"
-                        : [help] "+r" (help)
-                        : [mask] "i" (CR4_OSFXSR | CR4_OSXMMEXCPT)
+                    "mov %%cr4, %[help]\n"
+                    "or %[mask], %[help]\n"
+                    "mov %[help], %%cr4\n"
+                    : [help] "+r" (help)
+                    : [mask] "i" (CR4_OSFXSR | CR4_OSXMMEXCPT)
                 );
         }
@@ -128 +128 @@
                  * Check for AMD processor.
                  */
-                if ((info.cpuid_ebx == AMD_CPUID_EBX)
-                    && (info.cpuid_ecx == AMD_CPUID_ECX)
-                    && (info.cpuid_edx == AMD_CPUID_EDX))
+                if ((info.cpuid_ebx == AMD_CPUID_EBX) &&
+                    (info.cpuid_ecx == AMD_CPUID_ECX) &&
+                    (info.cpuid_edx == AMD_CPUID_EDX))
                         CPU->arch.vendor = VendorAMD;
 
@@ -136 +136 @@
                  * Check for Intel processor.
                  */
-                if ((info.cpuid_ebx == INTEL_CPUID_EBX)
-                    && (info.cpuid_ecx == INTEL_CPUID_ECX)
-                    && (info.cpuid_edx == INTEL_CPUID_EDX))
+                if ((info.cpuid_ebx == INTEL_CPUID_EBX) &&
+                    (info.cpuid_ecx == INTEL_CPUID_ECX) &&
+                    (info.cpuid_edx == INTEL_CPUID_EDX))
                         CPU->arch.vendor = VendorIntel;
 
@@ -148 +148 @@
 }
 
-void cpu_print_report(cpu_t* cpu)
+void cpu_print_report(cpu_t *cpu)
 {
         printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16
-                " MHz\n", cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
-                cpu->arch.model, cpu->arch.stepping, cpu->arch.id, cpu->frequency_mhz);
+            " MHz\n", cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
+            cpu->arch.model, cpu->arch.stepping, cpu->arch.id, cpu->frequency_mhz);
 }
 

kernel/arch/ia32/src/ia32.c

@@ -200 +200 @@
         outdev_t **ns16550_out_ptr = NULL;
 #endif
-        ns16550_instance_t *ns16550_instance
-            = ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
+        ns16550_instance_t *ns16550_instance =
+            ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
             ns16550_out_ptr);
         if (ns16550_instance) {

kernel/arch/ia64/src/drivers/ski.c

@@ -84 +84 @@
 
         asm volatile (
-                "mov r15 = %1\n"
-                "break 0x80000;;\n"  /* modifies r8 */
-                "mov %0 = r8;;\n"
-
-                : "=r" (ch)
-                : "i" (SKI_GETCHAR)
-                : "r15", "r8"
+            "mov r15 = %1\n"
+            "break 0x80000;;\n"  /* modifies r8 */
+            "mov %0 = r8;;\n"
+
+            : "=r" (ch)
+            : "i" (SKI_GETCHAR)
+            : "r15", "r8"
         );
 
@@ -143 +143 @@
 
         asm volatile (
-                "mov r15 = %0\n"
-                "break 0x80000\n"
-                :
-                : "i" (SKI_INIT_CONSOLE)
-                : "r15", "r8"
+            "mov r15 = %0\n"
+            "break 0x80000\n"
+            :
+            : "i" (SKI_INIT_CONSOLE)
+            : "r15", "r8"
         );
 
@@ -169 +169 @@
 {
         asm volatile (
-                "mov r15 = %[cmd]\n"
-                "mov r32 = %[ch]\n"   /* r32 is in0 */
-                "break 0x80000\n"     /* modifies r8 */
-                :
-                : [cmd] "i" (SKI_PUTCHAR), [ch] "r" (ch)
-                : "r15", "in0", "r8"
+            "mov r15 = %[cmd]\n"
+            "mov r32 = %[ch]\n"   /* r32 is in0 */
+            "break 0x80000\n"     /* modifies r8 */
+            :
+            : [cmd] "i" (SKI_PUTCHAR), [ch] "r" (ch)
+            : "r15", "in0", "r8"
         );
 }

kernel/arch/ia64/src/ia64.c

@@ -181 +181 @@
 
 #ifdef CONFIG_NS16550
-        ns16550_instance_t *ns16550_instance
-            = ns16550_init(NS16550_BASE, 0, NS16550_IRQ, NULL, NULL,
+        ns16550_instance_t *ns16550_instance =
+            ns16550_init(NS16550_BASE, 0, NS16550_IRQ, NULL, NULL,
             NULL);
         if (ns16550_instance) {
@@ -253 +253 @@
             (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value);
 
-        while (true);
+        while (true)
+                ;
 }
 
@@ -259 +260 @@
 {
         pio_write_8((ioport8_t *)0x64, 0xfe);
-        while (true);
+        while (true)
+                ;
 }
 

kernel/arch/ia64/src/interrupt.c

@@ -229 +229 @@
 {
         asm volatile (
-                "mov cr.eoi = r0 ;;"
+            "mov cr.eoi = r0 ;;"
         );
 }
@@ -245 +245 @@
         case INTERRUPT_SPURIOUS:
 #ifdef CONFIG_DEBUG
-                printf("cpu%d: spurious interrupt\n", CPU->id);
+                printf("cpu%d: spurious interrupt\n", CPU->id);
 #endif
                 break;

kernel/arch/mips32/include/arch/asm.h

@@ -57 +57 @@
 
         asm volatile (
-                "and %[base], $29, %[mask]\n"
-                : [base] "=r" (base)
-                : [mask] "r" (~(STACK_SIZE - 1))
+            "and %[base], $29, %[mask]\n"
+            : [base] "=r" (base)
+            : [mask] "r" (~(STACK_SIZE - 1))
         );
 

kernel/arch/mips32/include/arch/mm/tlb.h

@@ -82 +82 @@
                 unsigned : 2;       /* zero */
 #endif
-        } __attribute__ ((packed));
+        } __attribute__((packed));
         uint32_t value;
 } entry_lo_t;
@@ -97 +97 @@
                 unsigned vpn2 : 19;
 #endif
-        } __attribute__ ((packed));
+        } __attribute__((packed));
         uint32_t value;
 } entry_hi_t;
@@ -112 +112 @@
                 unsigned : 7;
 #endif
-        } __attribute__ ((packed));
+        } __attribute__((packed));
         uint32_t value;
 } page_mask_t;
@@ -127 +127 @@
                 unsigned p : 1;
 #endif
-        } __attribute__ ((packed));
+        } __attribute__((packed));
         uint32_t value;
 } tlb_index_t;

kernel/arch/mips32/src/debugger.c

@@ -102 +102 @@
         uint32_t value;
 } jmpinstr[] = {
-        {0xf3ff0000, 0x41000000},  /* BCzF */
-        {0xf3ff0000, 0x41020000},  /* BCzFL */
-        {0xf3ff0000, 0x41010000},  /* BCzT */
-        {0xf3ff0000, 0x41030000},  /* BCzTL */
-        {0xfc000000, 0x10000000},  /* BEQ */
-        {0xfc000000, 0x50000000},  /* BEQL */
-        {0xfc1f0000, 0x04010000},  /* BEQL */
-        {0xfc1f0000, 0x04110000},  /* BGEZAL */
-        {0xfc1f0000, 0x04130000},  /* BGEZALL */
-        {0xfc1f0000, 0x04030000},  /* BGEZL */
-        {0xfc1f0000, 0x1c000000},  /* BGTZ */
-        {0xfc1f0000, 0x5c000000},  /* BGTZL */
-        {0xfc1f0000, 0x18000000},  /* BLEZ */
-        {0xfc1f0000, 0x58000000},  /* BLEZL */
-        {0xfc1f0000, 0x04000000},  /* BLTZ */
-        {0xfc1f0000, 0x04100000},  /* BLTZAL */
-        {0xfc1f0000, 0x04120000},  /* BLTZALL */
-        {0xfc1f0000, 0x04020000},  /* BLTZL */
-        {0xfc000000, 0x14000000},  /* BNE */
-        {0xfc000000, 0x54000000},  /* BNEL */
-        {0xfc000000, 0x08000000},  /* J */
-        {0xfc000000, 0x0c000000},  /* JAL */
-        {0xfc1f07ff, 0x00000009},  /* JALR */
-        {0, 0}                     /* end of table */
+        { 0xf3ff0000, 0x41000000 },  /* BCzF */
+        { 0xf3ff0000, 0x41020000 },  /* BCzFL */
+        { 0xf3ff0000, 0x41010000 },  /* BCzT */
+        { 0xf3ff0000, 0x41030000 },  /* BCzTL */
+        { 0xfc000000, 0x10000000 },  /* BEQ */
+        { 0xfc000000, 0x50000000 },  /* BEQL */
+        { 0xfc1f0000, 0x04010000 },  /* BEQL */
+        { 0xfc1f0000, 0x04110000 },  /* BGEZAL */
+        { 0xfc1f0000, 0x04130000 },  /* BGEZALL */
+        { 0xfc1f0000, 0x04030000 },  /* BGEZL */
+        { 0xfc1f0000, 0x1c000000 },  /* BGTZ */
+        { 0xfc1f0000, 0x5c000000 },  /* BGTZL */
+        { 0xfc1f0000, 0x18000000 },  /* BLEZ */
+        { 0xfc1f0000, 0x58000000 },  /* BLEZL */
+        { 0xfc1f0000, 0x04000000 },  /* BLTZ */
+        { 0xfc1f0000, 0x04100000 },  /* BLTZAL */
+        { 0xfc1f0000, 0x04120000 },  /* BLTZALL */
+        { 0xfc1f0000, 0x04020000 },  /* BLTZL */
+        { 0xfc000000, 0x14000000 },  /* BNE */
+        { 0xfc000000, 0x54000000 },  /* BNEL */
+        { 0xfc000000, 0x08000000 },  /* J */
+        { 0xfc000000, 0x0c000000 },  /* JAL */
+        { 0xfc1f07ff, 0x00000009 },  /* JALR */
+        { 0, 0 }                     /* end of table */
 };
 
@@ -273 +273 @@
                             breakpoints[i].counter, (void *) breakpoints[i].address,
                             ((breakpoints[i].flags & BKPOINT_INPROG) ? "true" :
-                            "false"), ((breakpoints[i].flags & BKPOINT_ONESHOT)
-                            ? "true" : "false"), ((breakpoints[i].flags &
+                            "false"), ((breakpoints[i].flags & BKPOINT_ONESHOT) ?
+                            "true" : "false"), ((breakpoints[i].flags &
                             BKPOINT_FUNCCALL) ? "true" : "false"), symbol);
                 }
@@ -382 +382 @@
                 smc_coherence(cur->address);
 
-                if (! (cur->flags & BKPOINT_ONESHOT)) {
+                if (!(cur->flags & BKPOINT_ONESHOT)) {
                         /* Set Breakpoint on next instruction */
                         ((uint32_t *)cur->address)[1] = 0x0d;
@@ -422 +422 @@
         }
 
-        if ((cur) && (cur->address == fireaddr)
-            && ((cur->flags & BKPOINT_INPROG))) {
+        if ((cur) && (cur->address == fireaddr) &&
+            ((cur->flags & BKPOINT_INPROG))) {
                 /* Remove one-shot breakpoint */
                 if ((cur->flags & BKPOINT_ONESHOT))

kernel/arch/mips32/src/mach/msim/msim.c

@@ -94 +94 @@
          * interrupts.
          */
-        dsrlnin_instance_t *dsrlnin_instance
-            = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
+        dsrlnin_instance_t *dsrlnin_instance =
+            dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
         if (dsrlnin_instance) {
                 srln_instance_t *srln_instance = srln_init();

kernel/arch/mips32/src/mm/km.c

@@ -51 +51 @@
 bool km_is_non_identity_arch(uintptr_t addr)
 {
-        return iswithin(KM_MIPS32_KSSEG_START, KM_MIPS32_KSSEG_SIZE, addr, 1)
-            || iswithin(KM_MIPS32_KSEG3_START, KM_MIPS32_KSEG3_SIZE, addr, 1);
+        return iswithin(KM_MIPS32_KSSEG_START, KM_MIPS32_KSSEG_SIZE, addr, 1) ||
+            iswithin(KM_MIPS32_KSEG3_START, KM_MIPS32_KSEG3_SIZE, addr, 1);
 }
 

kernel/arch/ppc32/src/mm/pht.c

@@ -109 +109 @@
         /* Find colliding PTE in PTEG */
         for (i = 0; i < 8; i++) {
-                if ((phte[base + i].v)
-                    && (phte[base + i].vsid == vsid)
-                    && (phte[base + i].api == api)
-                    && (phte[base + i].h == 0)) {
+                if ((phte[base + i].v) &&
+                    (phte[base + i].vsid == vsid) &&
+                    (phte[base + i].api == api) &&
+                    (phte[base + i].h == 0)) {
                         found = true;
                         break;
@@ -134 +134 @@
                 /* Find colliding PTE in PTEG */
                 for (i = 0; i < 8; i++) {
-                        if ((phte[base2 + i].v)
-                            && (phte[base2 + i].vsid == vsid)
-                            && (phte[base2 + i].api == api)
-                            && (phte[base2 + i].h == 1)) {
+                        if ((phte[base2 + i].v) &&
+                            (phte[base2 + i].vsid == vsid) &&
+                            (phte[base2 + i].api == api) &&
+                            (phte[base2 + i].h == 1)) {
                                 found = true;
                                 base = base2;

kernel/arch/ppc32/src/ppc32.c

@@ -185 +185 @@
                 fb_scanline = *((uint32_t *) prop->value);
 
-        if ((fb_addr) && (fb_width > 0) && (fb_height > 0)
-            && (fb_scanline > 0) && (visual != VISUAL_UNKNOWN)) {
+        if ((fb_addr) && (fb_width > 0) && (fb_height > 0) &&
+            (fb_scanline > 0) && (visual != VISUAL_UNKNOWN)) {
                 fb_properties_t fb_prop = {
                         .addr = fb_addr,
@@ -301 +301 @@
 
         /* Unreachable */
-        while (true);
+        while (true)
+                ;
 }
 
@@ -321 +322 @@
 {
         // TODO
-        while (true);
+        while (true)
+                ;
 }
 

kernel/arch/sparc64/include/arch/asm.h

@@ -93 +93 @@
 
         asm volatile (
-                "rdpr %%pstate, %[v]\n"
-                : [v] "=r" (v)
+            "rdpr %%pstate, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -108 +108 @@
 {
         asm volatile (
-                "wrpr %[v], %[zero], %%pstate\n"
-                :: [v] "r" (v),
-                   [zero] "i" (0)
+            "wrpr %[v], %[zero], %%pstate\n"
+            :: [v] "r" (v),
+              [zero] "i" (0)
         );
 }
@@ -124 +124 @@
 
         asm volatile (
-                "rd %%tick_cmpr, %[v]\n"
-                : [v] "=r" (v)
+            "rd %%tick_cmpr, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -139 +139 @@
 {
         asm volatile (
-                "wr %[v], %[zero], %%tick_cmpr\n"
-                :: [v] "r" (v),
-                   [zero] "i" (0)
+            "wr %[v], %[zero], %%tick_cmpr\n"
+            :: [v] "r" (v),
+              [zero] "i" (0)
         );
 }
@@ -155 +155 @@
 
         asm volatile (
-                "rd %%asr25, %[v]\n"
-                : [v] "=r" (v)
+            "rd %%asr25, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -170 +170 @@
 {
         asm volatile (
-                "wr %[v], %[zero], %%asr25\n"
-                :: [v] "r" (v),
-                   [zero] "i" (0)
+            "wr %[v], %[zero], %%asr25\n"
+            :: [v] "r" (v),
+              [zero] "i" (0)
         );
 }
@@ -186 +186 @@
 
         asm volatile (
-                "rdpr %%tick, %[v]\n"
-                : [v] "=r" (v)
+            "rdpr %%tick, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -201 +201 @@
 {
         asm volatile (
-                "wrpr %[v], %[zero], %%tick\n"
-                :: [v] "r" (v),
-                   [zero] "i" (0)
+            "wrpr %[v], %[zero], %%tick\n"
+            :: [v] "r" (v),
+              [zero] "i" (0)
         );
 }
@@ -217 +217 @@
 
         asm volatile (
-                "rd %%fprs, %[v]\n"
-                : [v] "=r" (v)
+            "rd %%fprs, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -232 +232 @@
 {
         asm volatile (
-                "wr %[v], %[zero], %%fprs\n"
-                :: [v] "r" (v),
-                   [zero] "i" (0)
+            "wr %[v], %[zero], %%fprs\n"
+            :: [v] "r" (v),
+              [zero] "i" (0)
         );
 }
@@ -248 +248 @@
 
         asm volatile (
-                "rd %%softint, %[v]\n"
-                : [v] "=r" (v)
+            "rd %%softint, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -263 +263 @@
 {
         asm volatile (
-                "wr %[v], %[zero], %%softint\n"
-                :: [v] "r" (v),
-                   [zero] "i" (0)
+            "wr %[v], %[zero], %%softint\n"
+            :: [v] "r" (v),
+              [zero] "i" (0)
         );
 }
@@ -279 +279 @@
 {
         asm volatile (
-                "wr %[v], %[zero], %%clear_softint\n"
-                :: [v] "r" (v),
-                   [zero] "i" (0)
+            "wr %[v], %[zero], %%clear_softint\n"
+            :: [v] "r" (v),
+              [zero] "i" (0)
         );
 }
@@ -295 +295 @@
 {
         asm volatile (
-                "wr %[v], %[zero], %%set_softint\n"
-                :: [v] "r" (v),
-                   [zero] "i" (0)
+            "wr %[v], %[zero], %%set_softint\n"
+            :: [v] "r" (v),
+              [zero] "i" (0)
         );
 }
@@ -309 +309 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_enable(void) {
+NO_TRACE static inline ipl_t interrupts_enable(void)
+{
         pstate_reg_t pstate;
         uint64_t value = pstate_read();
@@ -328 +329 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_disable(void) {
+NO_TRACE static inline ipl_t interrupts_disable(void)
+{
         pstate_reg_t pstate;
         uint64_t value = pstate_read();
@@ -346 +348 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
+NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+{
         pstate_reg_t pstate;
 
@@ -361 +364 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void) {
+NO_TRACE static inline ipl_t interrupts_read(void)
+{
         return (ipl_t) pstate_read();
 }
@@ -390 +394 @@
 
         asm volatile (
-                "add %%sp, %[stack_bias], %[unbiased_sp]\n"
-                : [unbiased_sp] "=r" (unbiased_sp)
-                : [stack_bias] "i" (STACK_BIAS)
+            "add %%sp, %[stack_bias], %[unbiased_sp]\n"
+            : [unbiased_sp] "=r" (unbiased_sp)
+            : [stack_bias] "i" (STACK_BIAS)
         );
 
@@ -408 +412 @@
 
         asm volatile (
-                "rdpr %%ver, %[v]\n"
-                : [v] "=r" (v)
+            "rdpr %%ver, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -425 +429 @@
 
         asm volatile (
-                "rdpr %%tpc, %[v]\n"
-                : [v] "=r" (v)
+            "rdpr %%tpc, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -442 +446 @@
 
         asm volatile (
-                "rdpr %%tl, %[v]\n"
-                : [v] "=r" (v)
+            "rdpr %%tl, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -459 +463 @@
 
         asm volatile (
-                "rdpr %%tba, %[v]\n"
-                : [v] "=r" (v)
+            "rdpr %%tba, %[v]\n"
+            : [v] "=r" (v)
         );
 
@@ -474 +478 @@
 {
         asm volatile (
-                "wrpr %[v], %[zero], %%tba\n"
-                :: [v] "r" (v),
-                   [zero] "i" (0)
+            "wrpr %[v], %[zero], %%tba\n"
+            :: [v] "r" (v),
+              [zero] "i" (0)
         );
 }
@@ -494 +498 @@
 
         asm volatile (
-                "ldxa [%[va]] %[asi], %[v]\n"
-                : [v] "=r" (v)
-                : [va] "r" (va),
-                  [asi] "i" ((unsigned int) asi)
+            "ldxa [%[va]] %[asi], %[v]\n"
+            : [v] "=r" (v)
+            : [va] "r" (va),
+              [asi] "i" ((unsigned int) asi)
         );
 
@@ -513 +517 @@
 {
         asm volatile (
-                "stxa %[v], [%[va]] %[asi]\n"
-                :: [v] "r" (v),
-                   [va] "r" (va),
-                   [asi] "i" ((unsigned int) asi)
-                : "memory"
+            "stxa %[v], [%[va]] %[asi]\n"
+            :: [v] "r" (v),
+              [va] "r" (va),
+              [asi] "i" ((unsigned int) asi)
+            : "memory"
         );
 }

kernel/arch/sparc64/src/fpu_context.c

@@ -41 +41 @@
 {
         asm volatile (
-                "std %%f0, %0\n"
-                "std %%f2, %1\n"
-                "std %%f4, %2\n"
-                "std %%f6, %3\n"
-                "std %%f8, %4\n"
-                "std %%f10, %5\n"
-                "std %%f12, %6\n"
-                "std %%f14, %7\n"
-                "std %%f16, %8\n"
-                "std %%f18, %9\n"
-                "std %%f20, %10\n"
-                "std %%f22, %11\n"
-                "std %%f24, %12\n"
-                "std %%f26, %13\n"
-                "std %%f28, %14\n"
-                "std %%f30, %15\n"
-                : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]),
-                  "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]),
-                  "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]),
-                  "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15])
+            "std %%f0, %0\n"
+            "std %%f2, %1\n"
+            "std %%f4, %2\n"
+            "std %%f6, %3\n"
+            "std %%f8, %4\n"
+            "std %%f10, %5\n"
+            "std %%f12, %6\n"
+            "std %%f14, %7\n"
+            "std %%f16, %8\n"
+            "std %%f18, %9\n"
+            "std %%f20, %10\n"
+            "std %%f22, %11\n"
+            "std %%f24, %12\n"
+            "std %%f26, %13\n"
+            "std %%f28, %14\n"
+            "std %%f30, %15\n"
+            : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]),
+              "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]),
+              "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]),
+              "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15])
         );
 
@@ -69 +69 @@
 
         asm volatile (
-                "std %%f32, %0\n"
-                "std %%f34, %1\n"
-                "std %%f36, %2\n"
-                "std %%f38, %3\n"
-                "std %%f40, %4\n"
-                "std %%f42, %5\n"
-                "std %%f44, %6\n"
-                "std %%f46, %7\n"
-                "std %%f48, %8\n"
-                "std %%f50, %9\n"
-                "std %%f52, %10\n"
-                "std %%f54, %11\n"
-                "std %%f56, %12\n"
-                "std %%f58, %13\n"
-                "std %%f60, %14\n"
-                "std %%f62, %15\n"
-                : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]),
-                  "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
-                  "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
-                  "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
+            "std %%f32, %0\n"
+            "std %%f34, %1\n"
+            "std %%f36, %2\n"
+            "std %%f38, %3\n"
+            "std %%f40, %4\n"
+            "std %%f42, %5\n"
+            "std %%f44, %6\n"
+            "std %%f46, %7\n"
+            "std %%f48, %8\n"
+            "std %%f50, %9\n"
+            "std %%f52, %10\n"
+            "std %%f54, %11\n"
+            "std %%f56, %12\n"
+            "std %%f58, %13\n"
+            "std %%f60, %14\n"
+            "std %%f62, %15\n"
+            : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]),
+              "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
+              "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
+              "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
         );
 
@@ -97 +97 @@
 {
         asm volatile (
-                "ldd %0, %%f0\n"
-                "ldd %1, %%f2\n"
-                "ldd %2, %%f4\n"
-                "ldd %3, %%f6\n"
-                "ldd %4, %%f8\n"
-                "ldd %5, %%f10\n"
-                "ldd %6, %%f12\n"
-                "ldd %7, %%f14\n"
-                "ldd %8, %%f16\n"
-                "ldd %9, %%f18\n"
-                "ldd %10, %%f20\n"
-                "ldd %11, %%f22\n"
-                "ldd %12, %%f24\n"
-                "ldd %13, %%f26\n"
-                "ldd %14, %%f28\n"
-                "ldd %15, %%f30\n"
-                :
-                : "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]),
-                  "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]),
-                  "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]),
-                  "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15])
+            "ldd %0, %%f0\n"
+            "ldd %1, %%f2\n"
+            "ldd %2, %%f4\n"
+            "ldd %3, %%f6\n"
+            "ldd %4, %%f8\n"
+            "ldd %5, %%f10\n"
+            "ldd %6, %%f12\n"
+            "ldd %7, %%f14\n"
+            "ldd %8, %%f16\n"
+            "ldd %9, %%f18\n"
+            "ldd %10, %%f20\n"
+            "ldd %11, %%f22\n"
+            "ldd %12, %%f24\n"
+            "ldd %13, %%f26\n"
+            "ldd %14, %%f28\n"
+            "ldd %15, %%f30\n"
+            :
+            : "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]),
+              "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]),
+              "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]),
+              "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15])
         );
 
@@ -126 +126 @@
 
         asm volatile (
-                "ldd %0, %%f32\n"
-                "ldd %1, %%f34\n"
-                "ldd %2, %%f36\n"
-                "ldd %3, %%f38\n"
-                "ldd %4, %%f40\n"
-                "ldd %5, %%f42\n"
-                "ldd %6, %%f44\n"
-                "ldd %7, %%f46\n"
-                "ldd %8, %%f48\n"
-                "ldd %9, %%f50\n"
-                "ldd %10, %%f52\n"
-                "ldd %11, %%f54\n"
-                "ldd %12, %%f56\n"
-                "ldd %13, %%f58\n"
-                "ldd %14, %%f60\n"
-                "ldd %15, %%f62\n"
-                :
-                : "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]),
-                  "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
-                  "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
-                  "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
+            "ldd %0, %%f32\n"
+            "ldd %1, %%f34\n"
+            "ldd %2, %%f36\n"
+            "ldd %3, %%f38\n"
+            "ldd %4, %%f40\n"
+            "ldd %5, %%f42\n"
+            "ldd %6, %%f44\n"
+            "ldd %7, %%f46\n"
+            "ldd %8, %%f48\n"
+            "ldd %9, %%f50\n"
+            "ldd %10, %%f52\n"
+            "ldd %11, %%f54\n"
+            "ldd %12, %%f56\n"
+            "ldd %13, %%f58\n"
+            "ldd %14, %%f60\n"
+            "ldd %15, %%f62\n"
+            :
+            : "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]),
+              "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
+              "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
+              "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
         );
 

kernel/arch/sparc64/src/sun4v/md.c

@@ -62 +62 @@
         uint32_t name_blk_sz;           /**< Size in bytes of name block */
         uint32_t data_blk_sz;           /**< Size in bytes of data block */
-} __attribute__ ((packed)) md_header_t;
+} __attribute__((packed)) md_header_t;
 
 /** machine description element (in the node block) */
@@ -91 +91 @@
                 uint64_t val;
         } d;
-} __attribute__ ((packed)) md_element_t;
+} __attribute__((packed)) md_element_t;
 
 /** index of the element within the node block */
@@ -98 +98 @@
 /** buffer to which the machine description will be saved */
 static uint8_t mach_desc[MD_MAX_SIZE]
-         __attribute__ ((aligned (16)));
+    __attribute__((aligned(16)));
 
 
@@ -129 +129 @@
  */
 bool md_get_integer_property(md_node_t node, const char *key,
-        uint64_t *result)
+    uint64_t *result)
 {
         element_idx_t idx = node;
@@ -152 +152 @@
  */
 bool md_get_string_property(md_node_t node, const char *key,
-        const char **result)
+    const char **result)
 {
         md_header_t *md_header = (md_header_t *) mach_desc;