Changeset 3bacee1 in mainline for kernel/arch/mips32/src/mach/msim/msim.c

Timestamp:

2018-04-12T16:27:17Z (7 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

3cf22f9

Parents:

76d0981d

git-author:

Jiri Svoboda <jiri@…> (2018-04-11 19:25:33)

git-committer:

Jiri Svoboda <jiri@…> (2018-04-12 16:27:17)

Message:

Make ccheck-fix again and commit more good files.

File:

• kernel/arch/mips32/src/mach/msim/msim.c (modified) (1 diff)

kernel/arch/mips32/src/mach/msim/msim.c

@@ -94 +94 @@
          * interrupts.
          */
-        dsrlnin_instance_t *dsrlnin_instance
-            = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
+        dsrlnin_instance_t *dsrlnin_instance =
+            dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
         if (dsrlnin_instance) {
                 srln_instance_t *srln_instance = srln_init();