Changeset 22f7769 in mainline for arch


Ignore:
Timestamp:
2005-10-17T23:31:41Z (20 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
4b2c872d
Parents:
75eacab
Message:

Rename cpu_priority_{high|low|restore|read} functions to interrupts_{disable|enable|restore|read}.
Rename pri_t to ipl_t (Interrupt Priority Level).
Rename thread_t::pri to thread_t::priority.

Location:
arch
Files:
27 edited

Legend:

Unmodified
Added
Removed

  • arch/amd64/include/asm.h

    r75eacab r22f7769  
    8383}
    8484
    85 /** Set priority level low
     85/** Enable interrupts.
    8686 *
    8787 * Enable interrupts and return previous
    8888 * value of EFLAGS.
    89  */
    90 static inline pri_t cpu_priority_low(void) {
    91         pri_t v;
     89 *
     90 * @return Old interrupt priority level.
     91 */
     92static inline ipl_t interrupts_enable(void) {
     93        ipl_t v;
    9294        __asm__ volatile (
    9395                "pushfq\n"
    … …  
    99101}
    100102
    101 /** Set priority level high
     103/** Disable interrupts.
    102104 *
    103105 * Disable interrupts and return previous
    104106 * value of EFLAGS.
    105  */
    106 static inline pri_t cpu_priority_high(void) {
    107         pri_t v;
     107 *
     108 * @return Old interrupt priority level.
     109 */
     110static inline ipl_t interrupts_disable(void) {
     111        ipl_t v;
    108112        __asm__ volatile (
    109113                "pushfq\n"
    … …  
    115119}
    116120
    117 /** Restore priority level
     121/** Restore interrupt priority level.
    118122 *
    119123 * Restore EFLAGS.
    120  */
    121 static inline void cpu_priority_restore(pri_t pri) {
     124 *
     125 * @param ipl Saved interrupt priority level.
     126 */
     127static inline void interrupts_restore(ipl_t ipl) {
    122128        __asm__ volatile (
    123129                "pushq %0\n"
    124130                "popfq\n"
    125                 : : "r" (pri)
    126                 );
    127 }
    128 
    129 /** Return raw priority level
     131                : : "r" (ipl)
     132                );
     133}
     134
     135/** Return interrupt priority level.
    130136 *
    131137 * Return EFLAFS.
    132  */
    133 static inline pri_t cpu_priority_read(void) {
    134         pri_t v;
     138 *
     139 * @return Current interrupt priority level.
     140 */
     141static inline ipl_t interrupts_read(void) {
     142        ipl_t v;
    135143        __asm__ volatile (
    136144                "pushfq\n"

  • arch/amd64/include/context.h

    r75eacab r22f7769  
    5656    __u64 r15;
    5757
    58     pri_t pri;
     58    ipl_t ipl;
    5959} __attribute__ ((packed));
    6060

  • arch/amd64/include/types.h

    r75eacab r22f7769  
    4141typedef __u64 __address;
    4242
    43 /* Flags of processor (return value of cpu_priority_high()) */
    44 typedef __u64 pri_t;
     43/* Flags of processor (return value of interrupts_disable()) */
     44typedef __u64 ipl_t;
    4545
    4646typedef __u64 __native;

  • arch/amd64/src/interrupt.c

    r75eacab r22f7769  
    109109/*
    110110 * Called directly from the assembler code.
    111  * CPU is cpu_priority_high().
     111 * CPU is interrupts_disable()'d.
    112112 */
    113113void trap_dispatcher(__u8 n, __native stack[])

  • arch/amd64/src/userspace.c

    r75eacab r22f7769  
    4242void userspace(void)
    4343{
    44         pri_t pri;
     44        ipl_t ipl;
    4545       
    46         pri = cpu_priority_high();
     46        ipl = interrupts_disable();
    4747
    4848        __asm__ volatile (""
    … …  
    5858                          "pushq %%rsi;"
    5959                          "iretq;"
    60                           : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (pri), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));
     60                          : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (ipl), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));
    6161       
    6262        /* Unreachable */

  • arch/ia32/include/asm.h

    r75eacab r22f7769  
    132132static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
    133133
    134 /** Set priority level low
     134/** Enable interrupts.
    135135 *
    136136 * Enable interrupts and return previous
    137137 * value of EFLAGS.
    138  */
    139 static inline pri_t cpu_priority_low(void) {
    140         pri_t v;
     138 *
     139 * @return Old interrupt priority level.
     140 */
     141static inline ipl_t interrupts_enable(void) {
     142        ipl_t v;
    141143        __asm__ volatile (
    142144                "pushf\n\t"
    … …  
    148150}
    149151
    150 /** Set priority level high
     152/** Disable interrupts.
    151153 *
    152154 * Disable interrupts and return previous
    153155 * value of EFLAGS.
    154  */
    155 static inline pri_t cpu_priority_high(void) {
    156         pri_t v;
     156 *
     157 * @return Old interrupt priority level.
     158 */
     159static inline ipl_t interrupts_disable(void) {
     160        ipl_t v;
    157161        __asm__ volatile (
    158162                "pushf\n\t"
    … …  
    164168}
    165169
    166 /** Restore priority level
     170/** Restore interrupt priority level.
    167171 *
    168172 * Restore EFLAGS.
    169  */
    170 static inline void cpu_priority_restore(pri_t pri) {
     173 *
     174 * @param ipl Saved interrupt priority level.
     175 */
     176static inline void interrupts_restore(ipl_t ipl) {
    171177        __asm__ volatile (
    172178                "pushl %0\n\t"
    173179                "popf\n"
    174                 : : "r" (pri)
    175         );
    176 }
    177 
    178 /** Return raw priority level
    179  *
    180  * Return EFLAFS.
    181  */
    182 static inline pri_t cpu_priority_read(void) {
    183         pri_t v;
     180                : : "r" (ipl)
     181        );
     182}
     183
     184/** Return interrupt priority level.
     185 *
     186 * @return EFLAFS.
     187 */
     188static inline ipl_t interrupts_read(void) {
     189        ipl_t v;
    184190        __asm__ volatile (
    185191                "pushf\n\t"

  • arch/ia32/include/context.h

    r75eacab r22f7769  
    5353        __u32 edi;
    5454        __u32 ebp;
    55         __u32 pri;
     55        ipl_t ipl;
    5656} __attribute__ ((packed));
    5757

  • arch/ia32/include/types.h

    r75eacab r22f7769  
    4141typedef __u32 __address;
    4242
    43 typedef __u32 pri_t;
     43typedef __u32 ipl_t;
    4444
    4545typedef __u32 __native;

  • arch/ia32/src/drivers/ega.c

    r75eacab r22f7769  
    8181void ega_putchar(const char ch)
    8282{
    83         pri_t pri;
     83        ipl_t ipl;
    8484
    85         pri = cpu_priority_high();
     85        ipl = interrupts_disable();
    8686        spinlock_lock(&egalock);
    8787
    … …  
    102102
    103103        spinlock_unlock(&egalock);
    104         cpu_priority_restore(pri);
     104        interrupts_restore(ipl);
    105105}
    106106

  • arch/ia32/src/interrupt.c

    r75eacab r22f7769  
    8080/*
    8181 * Called directly from the assembler code.
    82  * CPU is cpu_priority_high().
     82 * CPU is interrupts_disable()'d.
    8383 */
    8484void trap_dispatcher(__u8 n, __native stack[])

  • arch/ia32/src/userspace.c

    r75eacab r22f7769  
    4242void userspace(void)
    4343{
    44         pri_t pri;
     44        ipl_t ipl;
    4545       
    46         pri = cpu_priority_high();
     46        ipl = interrupts_disable();
    4747
    4848        __asm__ volatile (
    … …  
    6161                "iret"
    6262                :
    63                 : "i" (selector(UDATA_DES) | PL_USER), "r" (USTACK_ADDRESS+(THREAD_STACK_SIZE)), "r" (pri), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)
     63                : "i" (selector(UDATA_DES) | PL_USER), "r" (USTACK_ADDRESS+(THREAD_STACK_SIZE)), "r" (ipl), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)
    6464                : "eax");
    6565       

  • arch/ia64/include/context.h

    r75eacab r22f7769  
    9696        __u64 pr;
    9797       
    98         pri_t pri;
     98        ipl_t ipl;
    9999} __attribute__ ((packed));
    100100

  • arch/ia64/include/types.h

    r75eacab r22f7769  
    4141typedef __u64 __address;
    4242
    43 typedef __u64 pri_t;
     43typedef __u64 ipl_t;
    4444
    4545typedef __u64 __native;

  • arch/ia64/src/context.S

    r75eacab r22f7769  
    135135         */
    136136
     137        /* TODO: ensure RSE lazy mode */
    137138        mov ar.bspstore = loc4
    138139        mov ar.rnat = loc5

  • arch/ia64/src/dummy.s

    r75eacab r22f7769  
    3636.global cpu_identify
    3737.global cpu_print_report
    38 .global cpu_priority_high
    39 .global cpu_priority_low
    40 .global cpu_priority_read
    41 .global cpu_priority_restore
     38.global interrupts_disable
     39.global interrupts_enable
     40.global interrupts_read
     41.global interrupts_restore
    4242.global cpu_sleep
    4343.global dummy
    … …  
    5353cpu_identify:
    5454cpu_print_report:
    55 cpu_priority_high:
    56 cpu_priority_low:
    57 cpu_priority_read:
    58 cpu_priority_restore:
     55interrupts_disable:
     56interrupts_enable:
     57interrupts_read:
     58interrupts_restore:
    5959cpu_sleep:
    6060fpu_init:

  • arch/mips32/include/context.h

    r75eacab r22f7769  
    6363        __u32 gp;
    6464
    65         __u32 pri;
     65        ipl_t ipl;
    6666};
    6767

  • arch/mips32/include/types.h

    r75eacab r22f7769  
    4646typedef __u32 __address;
    4747
    48 typedef __u32 pri_t;
     48typedef __u32 ipl_t;
    4949
    5050typedef __u32 __native;

  • arch/mips32/src/drivers/arc.c

    r75eacab r22f7769  
    176176{
    177177        __u32 cnt;
    178         pri_t pri;
     178        ipl_t ipl;
    179179
    180180        /* TODO: Should be spinlock? */
    181         pri = cpu_priority_high();
     181        ipl = interrupts_disable();
    182182        arc_entry->write(1, &ch, 1, &cnt);
    183         cpu_priority_restore(pri);
     183        interrupts_restore(ipl);
    184184       
    185185}

  • arch/mips32/src/exception.c

    r75eacab r22f7769  
    4747         * NOTE ON OPERATION ORDERING
    4848         *
    49          * On entry, cpu_priority_high() must be called before
     49         * On entry, interrupts_disable() must be called before
    5050         * exception bit is cleared.
    5151         */
    5252
    53         cpu_priority_high();
     53        interrupts_disable();
    5454        cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
    5555                                                cp0_status_um_bit));

  • arch/mips32/src/interrupt.c

    r75eacab r22f7769  
    5353}
    5454
    55 pri_t cpu_priority_high(void)
     55/** Disable interrupts.
     56 *
     57 * @return Old interrupt priority level.
     58 */
     59ipl_t interrupts_disable(void)
    5660{
    57         pri_t pri = (pri_t) cp0_status_read();
    58         cp0_status_write(pri & ~cp0_status_ie_enabled_bit);
    59         return pri;
     61        ipl_t ipl = (ipl_t) cp0_status_read();
     62        cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
     63        return ipl;
    6064}
    6165
    62 pri_t cpu_priority_low(void)
     66/** Enable interrupts.
     67 *
     68 * @return Old interrupt priority level.
     69 */
     70ipl_t interrupts_enable(void)
    6371{
    64         pri_t pri = (pri_t) cp0_status_read();
    65         cp0_status_write(pri | cp0_status_ie_enabled_bit);
    66         return pri;
     72        ipl_t ipl = (ipl_t) cp0_status_read();
     73        cp0_status_write(ipl | cp0_status_ie_enabled_bit);
     74        return ipl;
    6775}
    6876
    69 void cpu_priority_restore(pri_t pri)
     77/** Restore interrupt priority level.
     78 *
     79 * @param ipl Saved interrupt priority level.
     80 */
     81void interrupts_restore(ipl_t ipl)
    7082{
    71         cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit));
     83        cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
    7284}
    7385
    74 pri_t cpu_priority_read(void)
     86/** Read interrupt priority level.
     87 *
     88 * @return Current interrupt priority level.
     89 */
     90ipl_t interrupts_read(void)
    7591{
    7692        return cp0_status_read();

  • arch/mips32/src/mips32.c

    r75eacab r22f7769  
    5353{
    5454        /* It is not assumed by default */
    55         cpu_priority_high();
     55        interrupts_disable();
    5656
    5757        init_arc();

  • arch/mips32/src/mm/asid.c

    r75eacab r22f7769  
    4545asid_t asid_get(void)
    4646{
    47         pri_t pri;
     47        ipl_t ipl;
    4848        int i, j;
    4949        count_t min;
    … …  
    5151        min = (unsigned) -1;
    5252       
    53         pri = cpu_priority_high();
     53        ipl = interrupts_disable();
    5454        spinlock_lock(&asid_usage_lock);
    5555       
    … …  
    6666
    6767        spinlock_unlock(&asid_usage_lock);
    68         cpu_priority_restore(pri);
     68        interrupts_restore(ipl);
    6969
    7070        return i;
    … …  
    7979void asid_put(asid_t asid)
    8080{
    81         pri_t pri;
     81        ipl_t ipl;
    8282
    83         pri = cpu_priority_high();
     83        ipl = interrupts_disable();
    8484        spinlock_lock(&asid_usage_lock);
    8585
    … …  
    9090
    9191        spinlock_unlock(&asid_usage_lock);
    92         cpu_priority_restore(pri);
     92        interrupts_restore(ipl);
    9393}
    9494
    … …  
    104104{
    105105        bool has_conflicts = false;
    106         pri_t pri;
     106        ipl_t ipl;
    107107
    108108        ASSERT(asid != ASID_INVALID);
    109109
    110         pri = cpu_priority_high();
     110        ipl = interrupts_disable();
    111111        spinlock_lock(&asid_usage_lock);
    112112
    … …  
    115115
    116116        spinlock_unlock(&asid_usage_lock);
    117         cpu_priority_restore(pri);
     117        interrupts_restore(ipl);
    118118
    119119        return has_conflicts;

  • arch/mips32/src/mm/tlb.c

    r75eacab r22f7769  
    316316{
    317317        entry_hi_t hi;
    318         pri_t pri;
     318        ipl_t ipl;
    319319        int i; 
    320320       
    321321        ASSERT(asid != ASID_INVALID);
    322322
    323         pri = cpu_priority_high();
     323        ipl = interrupts_disable();
    324324       
    325325        for (i = 0; i < TLB_SIZE; i++) {
    … …  
    337337        }
    338338       
    339         cpu_priority_restore(pri);
     339        interrupts_restore(ipl);
    340340}
    341341

  • arch/mips32/src/mm/vm.c

    r75eacab r22f7769  
    4242{
    4343        entry_hi_t hi;
    44         pri_t pri;
     44        ipl_t ipl;
    4545       
    4646        hi.value = cp0_entry_hi_read();
    4747
    48         pri = cpu_priority_high();
     48        ipl = interrupts_disable();
    4949        spinlock_lock(&vm->lock);
    5050        hi.asid = vm->asid;
    5151        cp0_entry_hi_write(hi.value);   
    5252        spinlock_lock(&vm->unlock);
    53         cpu_priority_restore(pri);
     53        interrupts_restore(ipl);
    5454}

  • arch/ppc32/include/asm.h

    r75eacab r22f7769  
    3333#include <config.h>
    3434
    35 /** Set priority level low
     35/** Enable interrupts.
    3636 *
    3737 * Enable interrupts and return previous
    3838 * value of EE.
     39 *
     40 * @return Old interrupt priority level.
    3941 */
    40 static inline pri_t cpu_priority_low(void) {
    41         pri_t v;
    42         pri_t tmp;
     42static inline ipl_t interrupts_enable(void) {
     43        ipl_t v;
     44        ipl_t tmp;
    4345       
    4446        __asm__ volatile (
    … …  
    5254}
    5355
    54 /** Set priority level high
     56/** Disable interrupts.
    5557 *
    5658 * Disable interrupts and return previous
    5759 * value of EE.
     60 *
     61 * @return Old interrupt priority level.
    5862 */
    59 static inline pri_t cpu_priority_high(void) {
    60         pri_t v;
    61         pri_t tmp;
     63static inline ipl_t interrupts_disable(void) {
     64        ipl_t v;
     65        ipl_t tmp;
    6266       
    6367        __asm__ volatile (
    … …  
    7175}
    7276
    73 /** Restore priority level
     77/** Restore interrupt priority level.
    7478 *
    7579 * Restore EE.
     80 *
     81 * @param ipl Saved interrupt priority level.
    7682 */
    77 static inline void cpu_priority_restore(pri_t pri) {
    78         pri_t tmp;
     83static inline void interrupts_restore(ipl_t ipl) {
     84        ipl_t tmp;
    7985       
    8086        __asm__ volatile (
    … …  
    8591                "mtmsr %0\n"
    8692                "0:\n"
    87                 : "=r" (pri), "=r" (tmp)
    88                 : "0" (pri)
     93                : "=r" (ipl), "=r" (tmp)
     94                : "0" (ipl)
    8995        );
    9096}
    9197
    92 /** Return raw priority level
     98/** Return interrupt priority level.
    9399 *
    94100 * Return EE.
     101 *
     102 * @return Current interrupt priority level.
    95103 */
    96 static inline pri_t cpu_priority_read(void) {
    97         pri_t v;
     104static inline ipl_t interrupts_read(void) {
     105        ipl_t v;
    98106        __asm__ volatile (
    99107                "mfmsr %0\n"

  • arch/ppc32/include/context.h

    r75eacab r22f7769  
    6868        __u32 r31;
    6969        __u32 pc;
    70         pri_t pri;
     70        ipl_t ipl;
    7171} __attribute__ ((packed));
    7272

  • arch/ppc32/include/types.h

    r75eacab r22f7769  
    4141typedef __u32 __address;
    4242
    43 typedef __u32 pri_t;
     43typedef __u32 ipl_t;
    4444
    4545typedef __u32 __native;
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