source: mainline/arch/mips32/src/interrupt.c@ 22f7769

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 22f7769 was 22f7769, checked in by Jakub Jermar <jakub@…>, 20 years ago

Rename cpu_priority_{high|low|restore|read} functions to interrupts_{disable|enable|restore|read}.
Rename pri_t to ipl_t (Interrupt Priority Level).
Rename thread_t::pri to thread_t::priority.

  • Property mode set to 100644
File size: 3.6 KB
Line 
1/*
2 * Copyright (C) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/interrupt.h>
30#include <arch/types.h>
31#include <arch.h>
32#include <arch/cp0.h>
33#include <time/clock.h>
34#include <panic.h>
35#include <print.h>
36#include <symtab.h>
37#include <arch/drivers/arc.h>
38
39static void print_regdump(struct exception_regdump *pstate)
40{
41 char *pcsymbol = "";
42 char *rasymbol = "";
43
44 char *s = get_symtab_entry(pstate->epc);
45 if (s)
46 pcsymbol = s;
47 s = get_symtab_entry(pstate->ra);
48 if (s)
49 rasymbol = s;
50
51 printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol,
52 pstate->ra,rasymbol);
53}
54
55/** Disable interrupts.
56 *
57 * @return Old interrupt priority level.
58 */
59ipl_t interrupts_disable(void)
60{
61 ipl_t ipl = (ipl_t) cp0_status_read();
62 cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
63 return ipl;
64}
65
66/** Enable interrupts.
67 *
68 * @return Old interrupt priority level.
69 */
70ipl_t interrupts_enable(void)
71{
72 ipl_t ipl = (ipl_t) cp0_status_read();
73 cp0_status_write(ipl | cp0_status_ie_enabled_bit);
74 return ipl;
75}
76
77/** Restore interrupt priority level.
78 *
79 * @param ipl Saved interrupt priority level.
80 */
81void interrupts_restore(ipl_t ipl)
82{
83 cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
84}
85
86/** Read interrupt priority level.
87 *
88 * @return Current interrupt priority level.
89 */
90ipl_t interrupts_read(void)
91{
92 return cp0_status_read();
93}
94
95void interrupt(struct exception_regdump *pstate)
96{
97 __u32 cause;
98 int i;
99
100 /* decode interrupt number and process the interrupt */
101 cause = (cp0_cause_read() >> 8) &0xff;
102
103 for (i = 0; i < 8; i++) {
104 if (cause & (1 << i)) {
105 switch (i) {
106 case 0: /* SW0 - Software interrupt 0 */
107 cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
108 break;
109 case 1: /* SW1 - Software interrupt 1 */
110 cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
111 break;
112 case 2: /* IRQ0 */
113 case 3: /* IRQ1 */
114 case 4: /* IRQ2 */
115 case 5: /* IRQ3 */
116 case 6: /* IRQ4 */
117 print_regdump(pstate);
118 panic("unhandled interrupt %d\n", i);
119 break;
120 case TIMER_INTERRUPT:
121 /* clear timer interrupt & set new */
122 cp0_compare_write(cp0_count_read() + cp0_compare_value);
123 clock();
124 break;
125 }
126 }
127 }
128
129}
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