Ignore:
Timestamp:
2014-10-27T15:10:14Z (10 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
aef669b
Parents:
ec443d5
Message:

Let the fast MMU traps use exc_dispatch() in their slow-path.

In order to get proper exception accounting, the MMU related traps need
to go through the code in exc_dispatch(). To make this possible, we pass
the DTLB Tag Access register in istate_t in order to make way for the
trap type argument, which needs to be passed as the first argument to
exc_dispatch().

As a collateral change, this commit modifies the istate_t structure to
match the SPARC V9 ABI stack frame layout. It gives us a richer istate_t
with more information in it and also simplifies calculation of stack
offsets inside of preemptible_handler.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/src/trap/sun4u/trap_table.S

    rec443d5 rd70ebffe  
    6464        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    6565        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     66        clr %g5
    6667        PREEMPTIBLE_HANDLER exc_dispatch
    6768
    … …  
    7172instruction_access_error_tl0:
    7273        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     74        clr %g5
    7375        PREEMPTIBLE_HANDLER exc_dispatch
    7476
    … …  
    7880illegal_instruction_tl0:
    7981        mov TT_ILLEGAL_INSTRUCTION, %g2
     82        clr %g5
    8083        PREEMPTIBLE_HANDLER exc_dispatch
    8184
    … …  
    8588privileged_opcode_tl0:
    8689        mov TT_PRIVILEGED_OPCODE, %g2
     90        clr %g5
    8791        PREEMPTIBLE_HANDLER exc_dispatch
    8892
    … …  
    9296unimplemented_LDD_tl0:
    9397        mov TT_UNIMPLEMENTED_LDD, %g2
     98        clr %g5
    9499        PREEMPTIBLE_HANDLER exc_dispatch
    95100
    … …  
    99104unimplemented_STD_tl0:
    100105        mov TT_UNIMPLEMENTED_STD, %g2
     106        clr %g5
    101107        PREEMPTIBLE_HANDLER exc_dispatch
    102108
    … …  
    106112fp_disabled_tl0:
    107113        mov TT_FP_DISABLED, %g2
     114        clr %g5
    108115        PREEMPTIBLE_HANDLER exc_dispatch
    109116
    … …  
    113120fp_exception_ieee_754_tl0:
    114121        mov TT_FP_EXCEPTION_IEEE_754, %g2
     122        clr %g5
    115123        PREEMPTIBLE_HANDLER exc_dispatch
    116124
    … …  
    120128fp_exception_other_tl0:
    121129        mov TT_FP_EXCEPTION_OTHER, %g2
     130        clr %g5
    122131        PREEMPTIBLE_HANDLER exc_dispatch
    123132
    … …  
    127136tag_overflow_tl0:
    128137        mov TT_TAG_OVERFLOW, %g2
     138        clr %g5
    129139        PREEMPTIBLE_HANDLER exc_dispatch
    130140
    … …  
    140150division_by_zero_tl0:
    141151        mov TT_DIVISION_BY_ZERO, %g2
     152        clr %g5
    142153        PREEMPTIBLE_HANDLER exc_dispatch
    143154
    … …  
    148159        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    149160        mov TT_DATA_ACCESS_EXCEPTION, %g2
     161        clr %g5
    150162        PREEMPTIBLE_HANDLER exc_dispatch
    151163
    … …  
    155167data_access_error_tl0:
    156168        mov TT_DATA_ACCESS_ERROR, %g2
     169        clr %g5
    157170        PREEMPTIBLE_HANDLER exc_dispatch
    158171
    … …  
    162175mem_address_not_aligned_tl0:
    163176        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     177        clr %g5
    164178        PREEMPTIBLE_HANDLER exc_dispatch
    165179
    … …  
    169183LDDF_mem_address_not_aligned_tl0:
    170184        mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     185        clr %g5
    171186        PREEMPTIBLE_HANDLER exc_dispatch
    172187
    … …  
    176191STDF_mem_address_not_aligned_tl0:
    177192        mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     193        clr %g5
    178194        PREEMPTIBLE_HANDLER exc_dispatch
    179195
    … …  
    183199privileged_action_tl0:
    184200        mov TT_PRIVILEGED_ACTION, %g2
     201        clr %g5
    185202        PREEMPTIBLE_HANDLER exc_dispatch
    186203
    … …  
    190207LDQF_mem_address_not_aligned_tl0:
    191208        mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     209        clr %g5
    192210        PREEMPTIBLE_HANDLER exc_dispatch
    193211
    … …  
    197215STQF_mem_address_not_aligned_tl0:
    198216        mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     217        clr %g5
    199218        PREEMPTIBLE_HANDLER exc_dispatch
    200219
    … …  
    204223interrupt_level_1_handler_tl0:
    205224        mov TT_INTERRUPT_LEVEL_1, %g2
     225        clr %g5
    206226        PREEMPTIBLE_HANDLER exc_dispatch
    207227
    … …  
    211231interrupt_level_2_handler_tl0:
    212232        mov TT_INTERRUPT_LEVEL_2, %g2
     233        clr %g5
    213234        PREEMPTIBLE_HANDLER exc_dispatch
    214235
    … …  
    218239interrupt_level_3_handler_tl0:
    219240        mov TT_INTERRUPT_LEVEL_3, %g2
     241        clr %g5
    220242        PREEMPTIBLE_HANDLER exc_dispatch
    221243
    … …  
    225247interrupt_level_4_handler_tl0:
    226248        mov TT_INTERRUPT_LEVEL_4, %g2
     249        clr %g5
    227250        PREEMPTIBLE_HANDLER exc_dispatch
    228251
    … …  
    232255interrupt_level_5_handler_tl0:
    233256        mov TT_INTERRUPT_LEVEL_5, %g2
     257        clr %g5
    234258        PREEMPTIBLE_HANDLER exc_dispatch
    235259
    … …  
    239263interrupt_level_6_handler_tl0:
    240264        mov TT_INTERRUPT_LEVEL_6, %g2
     265        clr %g5
    241266        PREEMPTIBLE_HANDLER exc_dispatch
    242267
    … …  
    246271interrupt_level_7_handler_tl0:
    247272        mov TT_INTERRUPT_LEVEL_7, %g2
     273        clr %g5
    248274        PREEMPTIBLE_HANDLER exc_dispatch
    249275
    … …  
    253279interrupt_level_8_handler_tl0:
    254280        mov TT_INTERRUPT_LEVEL_8, %g2
     281        clr %g5
    255282        PREEMPTIBLE_HANDLER exc_dispatch
    256283
    … …  
    260287interrupt_level_9_handler_tl0:
    261288        mov TT_INTERRUPT_LEVEL_9, %g2
     289        clr %g5
    262290        PREEMPTIBLE_HANDLER exc_dispatch
    263291
    … …  
    267295interrupt_level_10_handler_tl0:
    268296        mov TT_INTERRUPT_LEVEL_10, %g2
     297        clr %g5
    269298        PREEMPTIBLE_HANDLER exc_dispatch
    270299
    … …  
    274303interrupt_level_11_handler_tl0:
    275304        mov TT_INTERRUPT_LEVEL_11, %g2
     305        clr %g5
    276306        PREEMPTIBLE_HANDLER exc_dispatch
    277307
    … …  
    281311interrupt_level_12_handler_tl0:
    282312        mov TT_INTERRUPT_LEVEL_12, %g2
     313        clr %g5
    283314        PREEMPTIBLE_HANDLER exc_dispatch
    284315
    … …  
    288319interrupt_level_13_handler_tl0:
    289320        mov TT_INTERRUPT_LEVEL_13, %g2
     321        clr %g5
    290322        PREEMPTIBLE_HANDLER exc_dispatch
    291323
    … …  
    295327interrupt_level_14_handler_tl0:
    296328        mov TT_INTERRUPT_LEVEL_14, %g2
     329        clr %g5
    297330        PREEMPTIBLE_HANDLER exc_dispatch
    298331
    … …  
    302335interrupt_level_15_handler_tl0:
    303336        mov TT_INTERRUPT_LEVEL_15, %g2
     337        clr %g5
    304338        PREEMPTIBLE_HANDLER exc_dispatch
    305339
    … …  
    309343interrupt_vector_trap_handler_tl0:
    310344        mov TT_INTERRUPT_VECTOR_TRAP, %g2
     345        clr %g5
    311346        PREEMPTIBLE_HANDLER exc_dispatch
    312347
    … …  
    377412.global trap_instruction_\cur\()_tl0
    378413trap_instruction_\cur\()_tl0:
     414        mov \cur, %g2
    379415        ba %xcc, trap_instruction_handler
    380         mov \cur, %g2
     416        clr %g5
    381417.endr
    382418
    … …  
    392428        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    393429        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     430        clr %g5
    394431        PREEMPTIBLE_HANDLER exc_dispatch
    395432
    … …  
    400437        wrpr %g0, 1, %tl
    401438        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     439        clr %g5
    402440        PREEMPTIBLE_HANDLER exc_dispatch
    403441
    … …  
    408446        wrpr %g0, 1, %tl
    409447        mov TT_ILLEGAL_INSTRUCTION, %g2
     448        clr %g5
    410449        PREEMPTIBLE_HANDLER exc_dispatch
    411450
    … …  
    422461        wrpr %g0, 1, %tl
    423462        mov TT_DIVISION_BY_ZERO, %g2
     463        clr %g5
    424464        PREEMPTIBLE_HANDLER exc_dispatch
    425465
    … …  
    431471        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    432472        mov TT_DATA_ACCESS_EXCEPTION, %g2
     473        clr %g5
    433474        PREEMPTIBLE_HANDLER exc_dispatch
    434475
    … …  
    439480        wrpr %g0, 1, %tl
    440481        mov TT_DATA_ACCESS_ERROR, %g2
     482        clr %g5
    441483        PREEMPTIBLE_HANDLER exc_dispatch
    442484
    … …  
    447489        wrpr %g0, 1, %tl
    448490        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     491        clr %g5
    449492        PREEMPTIBLE_HANDLER exc_dispatch
    450493
    … …  
    512555 *      %g1             Address of function to call if this is not a syscall.
    513556 *      %g2             First argument for the function.
     557 *      %g5             I/DTLB_TAG_ACCESS register if applicable.
    514558 *      %g6             Pre-set as kernel stack base if trap from userspace.
    515559 *      %g7             Pre-set as address of the userspace window buffer.
    516560 */
    517561.macro PREEMPTIBLE_HANDLER_TEMPLATE is_syscall
    518         /*
    519          * ASSERT(%tl == 1)
    520          */
    521         rdpr %tl, %g3
    522         cmp %g3, 1
    523         be %xcc, 1f
    524         nop
    525         ! this is for debugging, if we ever get here it will be easy to find
    526 0:      ba,a %xcc, 0b
    527 
    528 1:
    529562.if NOT(\is_syscall)
    530563        rdpr %tstate, %g3
    … …  
    544577        bnz %xcc, 0f                            ! ...skip setting of kernel stack and primary context
    545578        nop
    546        
    547579.endif
     580
    548581        /*
    549582         * Normal window spills will go to the userspace window buffer.
    … …  
    558591         * and the new window's %fp.
    559592         */
    560         save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     593        save %g6, -ISTATE_SIZE, %sp
    561594
    562595.if \is_syscall
    … …  
    590623        ba,a %xcc, 1f
    5916240:
    592         save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     625        save %sp, -ISTATE_SIZE, %sp
    593626
    594627        /*
    … …  
    612645.else
    613646        ! store the syscall number on the stack as 7th argument
    614         stx %g2, [%sp + STACK_WINDOW_SAVE_AREA_SIZE + STACK_BIAS + STACK_ARG6]
     647        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
    615648.endif
    616649
    617650        /*
    618          * Save TSTATE, TPC and TNPC aside.
     651         * Save TSTATE, TPC, TNPC and I/DTLB_TAG_ACCESS aside.
    619652         */
    620653        rdpr %tstate, %g1
    … …  
    623656        rd %y, %g4
    624657
    625         stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
    626         stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
    627         stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
     658        stx %g1, [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE]
     659        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_TPC]
     660        stx %g3, [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC]
     661        stx %g5, [%sp + STACK_BIAS + ISTATE_OFFSET_TLB_TAG_ACCESS]
    628662
    629663        /*
    630664         * Save the Y register.
    631          * This register is deprecated according to SPARC V9 specification
    632          * and is only present for backward compatibility with previous
    633          * versions of the SPARC architecture.
    634          * Surprisingly, gcc makes use of this register without a notice.
    635          */
    636         stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
     665         */
     666        stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y]
    637667       
    638668        wrpr %g0, 0, %tl
    … …  
    645675         */
    646676        call %l0
    647         add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
     677        add %sp, STACK_BIAS, %o1
    648678.else
    649679        /*
    … …  
    663693         * Read TSTATE, TPC and TNPC from saved copy.
    664694         */
    665         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
    666         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
    667         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
     695        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE], %g1
     696        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TPC], %g2
     697        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC], %g3
    668698
    669699        /*
    … …  
    686716         * Restore Y.
    687717         */
    688         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4
     718        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_Y], %g4
    689719        wr %g4, %y
    690720
    … …  
    726756         */
    727757        mov %sp, %g2
    728         stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
    729         stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
    730         stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
    731         stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
    732         stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
    733         stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
    734         stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
    735         stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
     758        stx %i0, [%sp + STACK_BIAS + ISTATE_OFFSET_O0]
     759        stx %i1, [%sp + STACK_BIAS + ISTATE_OFFSET_O1]
     760        stx %i2, [%sp + STACK_BIAS + ISTATE_OFFSET_O2]
     761        stx %i3, [%sp + STACK_BIAS + ISTATE_OFFSET_O3]
     762        stx %i4, [%sp + STACK_BIAS + ISTATE_OFFSET_O4]
     763        stx %i5, [%sp + STACK_BIAS + ISTATE_OFFSET_O5]
     764        stx %i6, [%sp + STACK_BIAS + ISTATE_OFFSET_O6]
     765        stx %i7, [%sp + STACK_BIAS + ISTATE_OFFSET_O7]
    736766        wrpr %l0, 0, %cwp
    737767        mov %g2, %sp
    738         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
    739         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
    740         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
    741         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
    742         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
    743         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
    744         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
    745         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
     768        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O0], %i0
     769        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O1], %i1
     770        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O2], %i2
     771        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O3], %i3
     772        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O4], %i4
     773        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O5], %i5
     774        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O6], %i6
     775        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O7], %i7
    746776
    747777        /*
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