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Changeset ae3ff9f5 in mainline for uspace/drv/block/ahci/ahci_hw.h


Ignore:
Timestamp:
2012-07-18T17:35:08Z (10 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial
Children:
7030bc9
Parents:
730dce77
Message:

import AHCI updates (comments, fixes) from Petr Jerman (lp:~petr-jerman/+junk/hos-ahci)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/block/ahci/ahci_hw.h

    r730dce77 rae3ff9f5  
    3535
    3636#include <sys/types.h>
     37
     38/*----------------------------------------------------------------------------*/
     39/*-- AHCI standard constants -------------------------------------------------*/
     40/*----------------------------------------------------------------------------*/
     41
     42/** AHCI standard 1.3 - maximum ports. */
     43#define AHCI_MAX_PORTS  32
    3744
    3845/*----------------------------------------------------------------------------*/
     
    198205typedef union {
    199206        struct {
    200                  /** Header layout. */
     207                /** Header layout. */
    201208                unsigned int hl : 7;
    202                 /** Multi function device. */
     209                /** Multi function device flag. */
    203210                unsigned int mfd : 1;
    204211        };
     
    281288typedef struct
    282289{
    283         /** Indicates the minimum grant time (in ? microseconds)
    284          * that the device wishes grant asserted.
     290        /** Indicates the minimum grant time that the device
     291         * wishes grant asserted.
    285292         */
    286293        uint8_t u8;
     
    297304/*-- AHCI Memory Registers ---------------------------------------------------*/
    298305/*----------------------------------------------------------------------------*/
     306
     307/** Number of pages for ahci memory registers. */
     308#define AHCI_MEMREGS_PAGES_COUNT  8
    299309
    300310/** AHCI Memory register Generic Host Control - HBA Capabilities. */
     
    364374} ahci_ghc_ghc_t;
    365375
     376/** AHCI GHC register offset. */
     377#define AHCI_GHC_GHC_REGISTER_OFFSET  1
     378
    366379/** AHCI Enable mask bit. */
    367380#define AHCI_GHC_GHC_AE  0x80000000
     
    377390        uint32_t u32;
    378391} ahci_ghc_is_t;
     392
     393/** AHCI GHC register offset. */
     394#define AHCI_GHC_IS_REGISTER_OFFSET  2 
    379395
    380396/** AHCI Memory register Ports implemented. */
     
    427443        /** Size of the transmit message buffer area in dwords. */
    428444        uint16_t sz;
    429         /* Offset of the transmit message buffer area in dwords
     445        /*
     446         * Offset of the transmit message buffer area in dwords
    430447         * from the beginning of ABAR
    431448         */
     
    462479                /** Activity LED hardware driven. */
    463480                unsigned int alhd : 1;
    464                 /** port multiplier support. */
     481                /** Port multiplier support. */
    465482                unsigned int pm : 1;
    466483                /** Reserved. */
     
    509526typedef struct
    510527{
    511         /** Host Capabilities. */
     528        /** Host Capabilities */
    512529        uint32_t cap;
    513         /** Global Host Control. */
     530        /** Global Host Control */
    514531        uint32_t ghc;
    515         /** Interrupt Status. */
     532        /** Interrupt Status */
    516533        uint32_t is;
    517         /** Ports Implemented. */
     534        /** Ports Implemented */
    518535        uint32_t pi;
    519         /** Version. */
     536        /** Version */
    520537        uint32_t vs;
    521         /** Command Completion Coalescing Control. */
     538        /** Command Completion Coalescing Control */
    522539        uint32_t ccc_ctl;
    523         /** Command Completion Coalsecing Ports. */
     540        /** Command Completion Coalescing Ports */
    524541        uint32_t ccc_ports;
    525         /** Enclosure Management Location. */
     542        /** Enclosure Management Location */
    526543        uint32_t em_loc;
    527         /** Enclosure Management Control. */
     544        /** Enclosure Management Control */
    528545        uint32_t em_ctl;
    529         /** Host Capabilities Extended. */
     546        /** Host Capabilities Extended */
    530547        uint32_t cap2;
    531         /** BIOS/OS Handoff Control and Status. */
     548        /** BIOS/OS Handoff Control and Status */
    532549        uint32_t bohc;
    533550} ahci_ghc_t;
     
    817834                 * Values:
    818835                 * 7h - fh Reserved,
    819                  * 6h Slumber - This shall cause the HBA to request a transition of the
    820                  *   interface to the Slumber state,
     836                 * 6h Slumber - This shall cause the HBA to request a transition
     837                 * of the interface to the Slumber state,
    821838                 * 3h - 5h Reserved,
    822                  * 2h Partial - This shall cause the HBA to request a transition of the
    823                  *   interface to the Partial state,
     839                 * 2h Partial - This shall cause the HBA to request a transition
     840                 * of the interface to the Partial state,
    824841                 * 1h Active,
    825842                 * 0h No-Op / Idle.
     
    856873                /** LBA Mid Register */
    857874                uint8_t lba_mr;
    858                 /**  LBA High Register */
     875                /** LBA High Register */
    859876                uint8_t lba_hr;
    860877        };
     
    876893        uint32_t u32;
    877894} ahci_port_ssts_t;
     895
     896/** Device detection active status. */
     897#define AHCI_PORT_SSTS_DET_ACTIVE  3
    878898
    879899/** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */
     
    10101030        ahci_ghc_t ghc;
    10111031        /** Reserved. */
    1012         uint8_t reserved[52];
     1032        uint32_t reserved[13];
    10131033        /** Reserved for NVMHCI. */
    1014         uint8_t reservedfornvmhci[64];
     1034        uint32_t reservedfornvmhci[16];
    10151035        /** Vendor Specific registers. */
    1016         uint8_t vendorspecificsregs[96];
     1036        uint32_t vendorspecificsregs[24];
    10171037        /** Ports. */
    10181038        ahci_port_t ports[32];
    10191039} ahci_memregs_t;
    10201040
    1021 /** AHCI Command header entry. */
     1041/** AHCI Command header entry.
     1042 *
     1043 * This structure is not an AHCI register.
     1044 *
     1045 */
    10221046typedef volatile struct {
    10231047        /** Flags. */
     
    10331057} ahci_cmdhdr_t;
    10341058
    1035 /** AHCI Command Physical Region Descriptor entry. */
     1059/** Clear Busy upon R_OK (C) flag. */
     1060#define AHCI_CMDHDR_FLAGS_CLEAR_BUSY_UPON_OK  0x0400
     1061
     1062/** Write operation flag. */
     1063#define AHCI_CMDHDR_FLAGS_WRITE  0x0040
     1064
     1065/** 2 DW length command flag. */
     1066#define AHCI_CMDHDR_FLAGS_2DWCMD  0x0002
     1067
     1068/** 5 DW length command flag. */
     1069#define AHCI_CMDHDR_FLAGS_5DWCMD  0x0005
     1070
     1071/** AHCI Command Physical Region Descriptor entry.
     1072 *
     1073 * This structure is not an AHCI register.
     1074 *
     1075 */
    10361076typedef volatile struct {
    10371077        /** Word aligned 32-bit data base address. */
     
    10451085        /** Reserved */
    10461086        unsigned int reserved2 : 9;
    1047         /** Interrupt on completion */
     1087        /** Set Interrupt on each operation completion */
    10481088        unsigned int ioc : 1;
    10491089} ahci_cmd_prdt_t;
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