Changeset ae3ff9f5 in mainline for uspace/drv/block/ahci/ahci_hw.h
- Timestamp:
- 2012-07-18T17:35:08Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 7030bc9
- Parents:
- 730dce77
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/block/ahci/ahci_hw.h
r730dce77 rae3ff9f5 35 35 36 36 #include <sys/types.h> 37 38 /*----------------------------------------------------------------------------*/ 39 /*-- AHCI standard constants -------------------------------------------------*/ 40 /*----------------------------------------------------------------------------*/ 41 42 /** AHCI standard 1.3 - maximum ports. */ 43 #define AHCI_MAX_PORTS 32 37 44 38 45 /*----------------------------------------------------------------------------*/ … … 198 205 typedef union { 199 206 struct { 200 207 /** Header layout. */ 201 208 unsigned int hl : 7; 202 /** Multi function device . */209 /** Multi function device flag. */ 203 210 unsigned int mfd : 1; 204 211 }; … … 281 288 typedef struct 282 289 { 283 /** Indicates the minimum grant time (in ? microseconds)284 * that the devicewishes grant asserted.290 /** Indicates the minimum grant time that the device 291 * wishes grant asserted. 285 292 */ 286 293 uint8_t u8; … … 297 304 /*-- AHCI Memory Registers ---------------------------------------------------*/ 298 305 /*----------------------------------------------------------------------------*/ 306 307 /** Number of pages for ahci memory registers. */ 308 #define AHCI_MEMREGS_PAGES_COUNT 8 299 309 300 310 /** AHCI Memory register Generic Host Control - HBA Capabilities. */ … … 364 374 } ahci_ghc_ghc_t; 365 375 376 /** AHCI GHC register offset. */ 377 #define AHCI_GHC_GHC_REGISTER_OFFSET 1 378 366 379 /** AHCI Enable mask bit. */ 367 380 #define AHCI_GHC_GHC_AE 0x80000000 … … 377 390 uint32_t u32; 378 391 } ahci_ghc_is_t; 392 393 /** AHCI GHC register offset. */ 394 #define AHCI_GHC_IS_REGISTER_OFFSET 2 379 395 380 396 /** AHCI Memory register Ports implemented. */ … … 427 443 /** Size of the transmit message buffer area in dwords. */ 428 444 uint16_t sz; 429 /* Offset of the transmit message buffer area in dwords 445 /* 446 * Offset of the transmit message buffer area in dwords 430 447 * from the beginning of ABAR 431 448 */ … … 462 479 /** Activity LED hardware driven. */ 463 480 unsigned int alhd : 1; 464 /** port multiplier support. */481 /** Port multiplier support. */ 465 482 unsigned int pm : 1; 466 483 /** Reserved. */ … … 509 526 typedef struct 510 527 { 511 /** Host Capabilities .*/528 /** Host Capabilities */ 512 529 uint32_t cap; 513 /** Global Host Control .*/530 /** Global Host Control */ 514 531 uint32_t ghc; 515 /** Interrupt Status .*/532 /** Interrupt Status */ 516 533 uint32_t is; 517 /** Ports Implemented .*/534 /** Ports Implemented */ 518 535 uint32_t pi; 519 /** Version .*/536 /** Version */ 520 537 uint32_t vs; 521 /** Command Completion Coalescing Control .*/538 /** Command Completion Coalescing Control */ 522 539 uint32_t ccc_ctl; 523 /** Command Completion Coal secing Ports.*/540 /** Command Completion Coalescing Ports */ 524 541 uint32_t ccc_ports; 525 /** Enclosure Management Location .*/542 /** Enclosure Management Location */ 526 543 uint32_t em_loc; 527 /** Enclosure Management Control .*/544 /** Enclosure Management Control */ 528 545 uint32_t em_ctl; 529 /** Host Capabilities Extended .*/546 /** Host Capabilities Extended */ 530 547 uint32_t cap2; 531 /** BIOS/OS Handoff Control and Status .*/548 /** BIOS/OS Handoff Control and Status */ 532 549 uint32_t bohc; 533 550 } ahci_ghc_t; … … 817 834 * Values: 818 835 * 7h - fh Reserved, 819 * 6h Slumber - This shall cause the HBA to request a transition of the820 * 836 * 6h Slumber - This shall cause the HBA to request a transition 837 * of the interface to the Slumber state, 821 838 * 3h - 5h Reserved, 822 * 2h Partial - This shall cause the HBA to request a transition of the823 * 839 * 2h Partial - This shall cause the HBA to request a transition 840 * of the interface to the Partial state, 824 841 * 1h Active, 825 842 * 0h No-Op / Idle. … … 856 873 /** LBA Mid Register */ 857 874 uint8_t lba_mr; 858 /** 875 /** LBA High Register */ 859 876 uint8_t lba_hr; 860 877 }; … … 876 893 uint32_t u32; 877 894 } ahci_port_ssts_t; 895 896 /** Device detection active status. */ 897 #define AHCI_PORT_SSTS_DET_ACTIVE 3 878 898 879 899 /** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */ … … 1010 1030 ahci_ghc_t ghc; 1011 1031 /** Reserved. */ 1012 uint 8_t reserved[52];1032 uint32_t reserved[13]; 1013 1033 /** Reserved for NVMHCI. */ 1014 uint 8_t reservedfornvmhci[64];1034 uint32_t reservedfornvmhci[16]; 1015 1035 /** Vendor Specific registers. */ 1016 uint 8_t vendorspecificsregs[96];1036 uint32_t vendorspecificsregs[24]; 1017 1037 /** Ports. */ 1018 1038 ahci_port_t ports[32]; 1019 1039 } ahci_memregs_t; 1020 1040 1021 /** AHCI Command header entry. */ 1041 /** AHCI Command header entry. 1042 * 1043 * This structure is not an AHCI register. 1044 * 1045 */ 1022 1046 typedef volatile struct { 1023 1047 /** Flags. */ … … 1033 1057 } ahci_cmdhdr_t; 1034 1058 1035 /** AHCI Command Physical Region Descriptor entry. */ 1059 /** Clear Busy upon R_OK (C) flag. */ 1060 #define AHCI_CMDHDR_FLAGS_CLEAR_BUSY_UPON_OK 0x0400 1061 1062 /** Write operation flag. */ 1063 #define AHCI_CMDHDR_FLAGS_WRITE 0x0040 1064 1065 /** 2 DW length command flag. */ 1066 #define AHCI_CMDHDR_FLAGS_2DWCMD 0x0002 1067 1068 /** 5 DW length command flag. */ 1069 #define AHCI_CMDHDR_FLAGS_5DWCMD 0x0005 1070 1071 /** AHCI Command Physical Region Descriptor entry. 1072 * 1073 * This structure is not an AHCI register. 1074 * 1075 */ 1036 1076 typedef volatile struct { 1037 1077 /** Word aligned 32-bit data base address. */ … … 1045 1085 /** Reserved */ 1046 1086 unsigned int reserved2 : 9; 1047 /** Interrupton completion */1087 /** Set Interrupt on each operation completion */ 1048 1088 unsigned int ioc : 1; 1049 1089 } ahci_cmd_prdt_t;
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