Changeset 730dce77 in mainline for uspace/drv/block/ahci/ahci_hw.h
- Timestamp:
- 2012-07-17T16:35:09Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 1bebadee, ae3ff9f5
- Parents:
- a00d555
- File:
-
- 1 edited
-
uspace/drv/block/ahci/ahci_hw.h (modified) (48 diffs)
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/block/ahci/ahci_hw.h
ra00d555 r730dce77 89 89 /** Indicates what device number assigned by the vendor */ 90 90 uint16_t deviceid; 91 } __attribute__((packed))ahci_pcireg_id_t;91 } ahci_pcireg_id_t; 92 92 93 93 /** AHCI PCI register Command. */ … … 120 120 /** Reserved. */ 121 121 unsigned int reserved : 5; 122 } __attribute__((packed));122 }; 123 123 uint16_t u16; 124 } __attribute__((packed))ahci_pcireg_cmd_t;124 } ahci_pcireg_cmd_t; 125 125 126 126 /** AHCI PCI register Command - Interrupt Disable bit. */ … … 159 159 /** Detected parity error. */ 160 160 unsigned int dpe : 1; 161 } __attribute__((packed));161 }; 162 162 uint16_t u16; 163 } __attribute__((packed))ahci_pcireg_sts_t;163 } ahci_pcireg_sts_t; 164 164 165 165 /** AHCI PCI register Revision ID. */ … … 167 167 /** Indicates stepping of the HBA hardware. */ 168 168 uint8_t u8; 169 } __attribute__((packed))ahci_pcireg_rid_t;169 } ahci_pcireg_rid_t; 170 170 171 171 /** AHCI PCI register Class Codes. */ … … 179 179 /** Value 01 indicates that is a mass storage device. */ 180 180 uint8_t bcc; 181 } __attribute__((packed))ahci_pcireg_cc_t_t;181 } ahci_pcireg_cc_t_t; 182 182 183 183 /** AHCI PCI register Cache Line Size. */ 184 184 typedef struct { 185 /** Cache line size for use with the memory write and invalidate command. */185 /** Cache line size for use with the memory write and invalidate command. */ 186 186 uint8_t u8; 187 } __attribute__((packed))ahci_pcireg_cls_t;187 } ahci_pcireg_cls_t; 188 188 189 189 /** AHCI PCI register Master Latency Timer. */ … … 193 193 */ 194 194 uint8_t u8; 195 } __attribute__((packed))ahci_pcireg_mlt_t;195 } ahci_pcireg_mlt_t; 196 196 197 197 /** AHCI PCI register Header Type. */ … … 202 202 /** Multi function device. */ 203 203 unsigned int mfd : 1; 204 } __attribute__((packed));204 }; 205 205 uint8_t u8; 206 } __attribute__((packed))ahci_pciregs_htype_t;206 } ahci_pciregs_htype_t; 207 207 208 208 /** AHCI PCI register Built in self test. */ … … 221 221 /** BIST capable. */ 222 222 unsigned int bc : 1; 223 } __attribute__((packed));223 }; 224 224 uint8_t u8; 225 } __attribute__((packed))ahci_pciregs_bist_t;225 } ahci_pciregs_bist_t; 226 226 227 227 /** AHCI PCI register AHCI Base Address <BAR 5>. */ … … 240 240 /** Base address of registry memory space. */ 241 241 unsigned int ba : 19; 242 } __attribute__((packed));243 uint32_t u32; 244 } __attribute__((packed))ahci_pciregs_abar_t;242 }; 243 uint32_t u32; 244 } ahci_pciregs_abar_t; 245 245 246 246 /** AHCI PCI register Subsystem Identifiers. */ … … 251 251 /** Sub system identifier. */ 252 252 uint8_t ssid; 253 } __attribute__((packed))ahci_pcireg_ss_t;253 } ahci_pcireg_ss_t; 254 254 255 255 /** AHCI PCI registers Expansion ROM Base Address. */ … … 258 258 /** Indicates the base address of the HBA expansion ROM. */ 259 259 uint32_t u32; 260 } __attribute__((packed))ahci_pcireg_erom_t;260 } ahci_pcireg_erom_t; 261 261 262 262 /** AHCI PCI register Capabilities Pointer. */ … … 265 265 /** Indicates the first capability pointer offset. */ 266 266 uint8_t u8; 267 } __attribute__((packed))ahci_pcireg_cap_t;267 } ahci_pcireg_cap_t; 268 268 269 269 /** AHCI PCI register Interrupt Information. */ … … 276 276 /** This indicates the interrupt pin the HBA uses. */ 277 277 uint8_t ipin; 278 } __attribute__((packed))ahci_pcireg_intr;278 } ahci_pcireg_intr; 279 279 280 280 /** AHCI PCI register Min Grant (Optional). */ … … 285 285 */ 286 286 uint8_t u8; 287 } __attribute__((packed))ahci_pcireg_mgnt_t;287 } ahci_pcireg_mgnt_t; 288 288 289 289 /** AHCI PCI register Max Latency (Optional). */ … … 292 292 /** Indicates the maximum latency that the device can withstand. */ 293 293 uint8_t u8; 294 } __attribute__((packed))ahci_pcireg_mlat_t;294 } ahci_pcireg_mlat_t; 295 295 296 296 /*----------------------------------------------------------------------------*/ … … 343 343 /** Supports 64-bit Addressing. */ 344 344 unsigned int s64a : 1; 345 } __attribute__((packed));346 uint32_t u32; 347 } __attribute__((packed))ahci_ghc_cap_t;345 }; 346 uint32_t u32; 347 } ahci_ghc_cap_t; 348 348 349 349 /** AHCI Memory register Generic Host Control Global Host Control. */ … … 360 360 /** AHCI Enable. */ 361 361 unsigned int ae : 1; 362 } __attribute__((packed));363 uint32_t u32; 364 } __attribute__((packed))ahci_ghc_ghc_t;362 }; 363 uint32_t u32; 364 } ahci_ghc_ghc_t; 365 365 366 366 /** AHCI Enable mask bit. */ … … 376 376 */ 377 377 uint32_t u32; 378 } __attribute__((packed))ahci_ghc_is_t;378 } ahci_ghc_is_t; 379 379 380 380 /** AHCI Memory register Ports implemented. */ … … 384 384 */ 385 385 uint32_t u32; 386 } __attribute__((packed))ahci_ghc_pi_t;386 } ahci_ghc_pi_t; 387 387 388 388 /** AHCI Memory register AHCI version. */ … … 392 392 /** Indicates the major version */ 393 393 uint16_t mjr; 394 } __attribute__((packed))ahci_ghc_vs_t;394 } ahci_ghc_vs_t; 395 395 396 396 /** AHCI Memory register Command completion coalesce control. */ … … 409 409 /** Timeout value in ms. */ 410 410 uint16_t tv; 411 } __attribute__((packed));412 uint32_t u32; 413 } __attribute__((packed))ahci_ghc_ccc_ctl_t;411 }; 412 uint32_t u32; 413 } ahci_ghc_ccc_ctl_t; 414 414 415 415 /** AHCI Memory register Command completion coalescing ports. */ … … 420 420 */ 421 421 uint32_t u32; 422 } __attribute__((packed))ahci_ghc_ccc_ports_t;422 } ahci_ghc_ccc_ports_t; 423 423 424 424 /** AHCI Memory register Enclosure management location. */ … … 431 431 */ 432 432 uint16_t ofst; 433 } __attribute__((packed))ahci_ghc_em_loc;433 } ahci_ghc_em_loc; 434 434 435 435 /** AHCI Memory register Enclosure management control. */ … … 466 466 /** Reserved. */ 467 467 unsigned int reserved4 : 4; 468 } __attribute__((packed));469 uint32_t u32; 470 } __attribute__((packed))ahci_ghc_em_ctl_t;468 }; 469 uint32_t u32; 470 } ahci_ghc_em_ctl_t; 471 471 472 472 /** AHCI Memory register HBA capatibilities extended. */ … … 483 483 /** Reserved. */ 484 484 unsigned int reserved : 29; 485 } __attribute__((packed));486 uint32_t u32; 487 } __attribute__((packed))ahci_ghc_cap2_t;485 }; 486 uint32_t u32; 487 } ahci_ghc_cap2_t; 488 488 489 489 /** AHCI Memory register BIOS/OS Handoff control and status. */ … … 502 502 /** Reserved. */ 503 503 unsigned int reserved : 27; 504 } __attribute__((packed));505 uint32_t u32; 506 } __attribute__((packed))ahci_ghc_bohc_t;504 }; 505 uint32_t u32; 506 } ahci_ghc_bohc_t; 507 507 508 508 /** AHCI Memory register Generic Host Control. */ … … 531 531 /** BIOS/OS Handoff Control and Status. */ 532 532 uint32_t bohc; 533 } __attribute__((packed))ahci_ghc_t;533 } ahci_ghc_t; 534 534 535 535 /** AHCI Memory register Port x Command List Base Address. */ … … 545 545 */ 546 546 unsigned int clb : 22; 547 } __attribute__((packed));548 uint32_t u32; 549 } __attribute__((packed))ahci_port_clb_t;547 }; 548 uint32_t u32; 549 } ahci_port_clb_t; 550 550 551 551 /** AHCI Memory register Port x Command List Base Address Upper 32-Bits. */ … … 557 557 */ 558 558 uint32_t u32; 559 } __attribute__((packed))ahci_port_clbu_t;559 } ahci_port_clbu_t; 560 560 561 561 /** AHCI Memory register Port x FIS Base Address. */ … … 563 563 struct { 564 564 /** Reserved. */ 565 u int8_t reserved;565 unsigned int reserved : 8; 566 566 /** FIS Base Address (FB) - Indicates the 32-bit base physical address 567 567 * for received FISes. The structure pointed to by this address range … … 572 572 */ 573 573 unsigned int fb : 24; 574 } __attribute__((packed));575 uint32_t u32; 576 } __attribute__((packed))ahci_port_fb_t;574 }; 575 uint32_t u32; 576 } ahci_port_fb_t; 577 577 578 578 /** AHCI Memory register Port x FIS Base Address Upper 32-Bits. */ … … 583 583 */ 584 584 uint32_t u32; 585 } __attribute__((packed))ahci_port_fbu_t;585 } ahci_port_fbu_t; 586 586 587 587 /** AHCI Memory register Port x Interrupt Status. */ … … 626 626 /** Cold Port Detect Status. */ 627 627 unsigned int cpds : 1; 628 } __attribute__((packed));629 uint32_t u32; 630 } __attribute__((packed))ahci_port_is_t;628 }; 629 uint32_t u32; 630 } ahci_port_is_t; 631 631 632 632 #define AHCI_PORT_IS_DHRS (1 << 0) … … 763 763 /** Cold Port Detect Enable. */ 764 764 unsigned int cpde : 1; 765 } __attribute__((packed));766 uint32_t u32; 767 } __attribute__((packed))ahci_port_ie_t;765 }; 766 uint32_t u32; 767 } ahci_port_ie_t; 768 768 769 769 /** AHCI Memory register Port x Command and Status. */ … … 826 826 */ 827 827 unsigned int icc : 4; 828 } __attribute__((packed));829 uint32_t u32; 830 } __attribute__((packed))ahci_port_cmd_t;828 }; 829 uint32_t u32; 830 } ahci_port_cmd_t; 831 831 832 832 /** AHCI Memory register Port x Task File Data. */ … … 843 843 /** Reserved. */ 844 844 uint16_t reserved; 845 } __attribute__((packed));846 uint32_t u32; 847 } __attribute__((packed))ahci_port_tfd_t;845 }; 846 uint32_t u32; 847 } ahci_port_tfd_t; 848 848 849 849 /** AHCI Memory register Port x Signature. */ … … 858 858 /** LBA High Register */ 859 859 uint8_t lba_hr; 860 } __attribute__((packed));861 uint32_t u32; 862 } __attribute__((packed))ahci_port_sig_t;860 }; 861 uint32_t u32; 862 } ahci_port_sig_t; 863 863 864 864 /** AHCI Memory register Port x Serial ATA Status (SCR0: SStatus). */ … … 873 873 /** Reserved. */ 874 874 unsigned int reserved : 20; 875 } __attribute__((packed));876 uint32_t u32; 877 } __attribute__((packed))ahci_port_ssts_t;875 }; 876 uint32_t u32; 877 } ahci_port_ssts_t; 878 878 879 879 /** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */ … … 888 888 /** Reserved. */ 889 889 unsigned int reserved : 20; 890 } __attribute__((packed));891 uint32_t u32; 892 } __attribute__((packed))ahci_port_sctl_t;890 }; 891 uint32_t u32; 892 } ahci_port_sctl_t; 893 893 894 894 /** AHCI Memory register Port x Port x Serial ATA Error (SCR1: SError). */ … … 904 904 */ 905 905 uint16_t diag; 906 } __attribute__((packed))ahci_port_serr_t;906 } ahci_port_serr_t; 907 907 908 908 /** AHCI Memory register Port x Serial ATA Active (SCR3: SActive). */ … … 913 913 */ 914 914 uint32_t u32; 915 } __attribute__((packed))ahci_port_sact_t;915 } ahci_port_sact_t; 916 916 917 917 /** AHCI Memory register Port x Command Issue. */ … … 921 921 */ 922 922 uint32_t u32; 923 } __attribute__((packed))ahci_port_ci_t;923 } ahci_port_ci_t; 924 924 925 925 /** AHCI Memory register Port x Serial ATA Notification … … 934 934 /** Reserved. */ 935 935 uint16_t reserved; 936 } __attribute__((packed))ahci_port_sntf_t;936 } ahci_port_sntf_t; 937 937 938 938 /** AHCI Memory register Port x FIS-based Switching Control. … … 958 958 /** Reserved. */ 959 959 unsigned int reserved2 : 1; 960 } __attribute__((packed));961 uint32_t u32; 962 } __attribute__((packed))ahci_port_fbs_t;960 }; 961 uint32_t u32; 962 } ahci_port_fbs_t; 963 963 964 964 /** AHCI Memory register Port. */ … … 1003 1003 /** Port x Vendor Specific. */ 1004 1004 uint32_t pxvs[4]; 1005 } __attribute__((packed))ahci_port_t;1005 } ahci_port_t; 1006 1006 1007 1007 /** AHCI Memory Registers. */ … … 1017 1017 /** Ports. */ 1018 1018 ahci_port_t ports[32]; 1019 } __attribute__((packed))ahci_memregs_t;1019 } ahci_memregs_t; 1020 1020 1021 1021 /** AHCI Command header entry. */ … … 1031 1031 /** Command Table Descriptor Base Address Upper 32-bits. */ 1032 1032 uint32_t cmdtableu; 1033 } __attribute__((packed))ahci_cmdhdr_t;1033 } ahci_cmdhdr_t; 1034 1034 1035 1035 /** AHCI Command Physical Region Descriptor entry. */ … … 1047 1047 /** Interrupt on completion */ 1048 1048 unsigned int ioc : 1; 1049 } __attribute__((packed))ahci_cmd_prdt_t;1049 } ahci_cmd_prdt_t; 1050 1050 1051 1051 #endif
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