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Changeset 730dce77 in mainline


Ignore:
Timestamp:
2012-07-17T16:35:09Z (10 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial
Children:
1bebadee, ae3ff9f5
Parents:
a00d555
Message:

get rid of the packed structure attribute (there should be no unwanted padding present)
this fixes compilation for arm32

Location:
uspace/drv/block/ahci
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/block/ahci/ahci.c

    ra00d555 r730dce77  
    601601        if ((sata->invalid_device) || (ahci_port_is_error(pxis))) {
    602602                ddf_msg(LVL_ERROR,
    603                     "%s: Unrecoverable error during fpdma write", sata->model);
     603                    "%s: Unrecoverable error during FPDMA write", sata->model);
    604604                return EINTR;
    605605        }
  • uspace/drv/block/ahci/ahci_hw.h

    ra00d555 r730dce77  
    8989        /** Indicates what device number assigned by the vendor */
    9090        uint16_t deviceid;
    91 } __attribute__((packed)) ahci_pcireg_id_t;
     91} ahci_pcireg_id_t;
    9292
    9393/** AHCI PCI register Command. */
     
    120120                /** Reserved. */
    121121                unsigned int reserved : 5;
    122         } __attribute__((packed));
     122        };
    123123        uint16_t u16;
    124 } __attribute__((packed)) ahci_pcireg_cmd_t;
     124} ahci_pcireg_cmd_t;
    125125
    126126/** AHCI PCI register Command - Interrupt Disable bit. */
     
    159159                /** Detected parity error. */
    160160                unsigned int dpe : 1;
    161         } __attribute__((packed));
     161        };
    162162        uint16_t u16;
    163 } __attribute__((packed)) ahci_pcireg_sts_t;
     163} ahci_pcireg_sts_t;
    164164
    165165/** AHCI PCI register Revision ID. */
     
    167167        /** Indicates stepping of the HBA hardware. */
    168168        uint8_t u8;
    169 } __attribute__((packed)) ahci_pcireg_rid_t;
     169} ahci_pcireg_rid_t;
    170170
    171171/** AHCI PCI register Class Codes. */
     
    179179        /** Value 01 indicates that is a mass storage device. */
    180180        uint8_t bcc;
    181 } __attribute__((packed)) ahci_pcireg_cc_t_t;
     181} ahci_pcireg_cc_t_t;
    182182
    183183/** AHCI PCI register Cache Line Size. */
    184184typedef struct {
    185         /** Cache line sizefor use with the memory write and invalidate command. */
     185        /** Cache line size for use with the memory write and invalidate command. */
    186186        uint8_t u8;
    187 } __attribute__((packed)) ahci_pcireg_cls_t;
     187} ahci_pcireg_cls_t;
    188188
    189189/** AHCI PCI register Master Latency Timer. */
     
    193193         */
    194194        uint8_t u8;
    195 } __attribute__((packed)) ahci_pcireg_mlt_t;
     195} ahci_pcireg_mlt_t;
    196196
    197197/** AHCI PCI register Header Type. */
     
    202202                /** Multi function device. */
    203203                unsigned int mfd : 1;
    204         } __attribute__((packed));
     204        };
    205205        uint8_t u8;
    206 } __attribute__((packed)) ahci_pciregs_htype_t;
     206} ahci_pciregs_htype_t;
    207207
    208208/** AHCI PCI register Built in self test. */
     
    221221        /** BIST capable. */
    222222        unsigned int bc : 1;
    223         }  __attribute__((packed));
     223        };
    224224        uint8_t u8;
    225 } __attribute__((packed)) ahci_pciregs_bist_t;
     225} ahci_pciregs_bist_t;
    226226
    227227/** AHCI PCI register AHCI Base Address <BAR 5>. */
     
    240240                /** Base address of registry memory space. */
    241241                unsigned int ba : 19;
    242         }  __attribute__((packed));
    243         uint32_t u32;
    244 }  __attribute__((packed)) ahci_pciregs_abar_t;
     242        };
     243        uint32_t u32;
     244} ahci_pciregs_abar_t;
    245245
    246246/** AHCI PCI register Subsystem Identifiers. */
     
    251251        /** Sub system identifier. */
    252252        uint8_t ssid;
    253 } __attribute__((packed)) ahci_pcireg_ss_t;
     253} ahci_pcireg_ss_t;
    254254
    255255/** AHCI PCI registers Expansion ROM Base Address. */
     
    258258        /** Indicates the base address of the HBA expansion ROM. */
    259259        uint32_t u32;
    260 } __attribute__((packed)) ahci_pcireg_erom_t;
     260} ahci_pcireg_erom_t;
    261261
    262262/** AHCI PCI register Capabilities Pointer. */
     
    265265        /** Indicates the first capability pointer offset. */
    266266        uint8_t u8;
    267 } __attribute__((packed)) ahci_pcireg_cap_t;
     267} ahci_pcireg_cap_t;
    268268
    269269/** AHCI PCI register Interrupt Information. */
     
    276276        /** This indicates the interrupt pin the HBA uses. */
    277277        uint8_t ipin;
    278 } __attribute__((packed)) ahci_pcireg_intr;
     278} ahci_pcireg_intr;
    279279
    280280/** AHCI PCI register Min Grant (Optional). */
     
    285285         */
    286286        uint8_t u8;
    287 } __attribute__((packed)) ahci_pcireg_mgnt_t;
     287} ahci_pcireg_mgnt_t;
    288288
    289289/** AHCI PCI register Max Latency (Optional). */
     
    292292        /** Indicates the maximum latency that the device can withstand. */
    293293        uint8_t u8;
    294 } __attribute__((packed)) ahci_pcireg_mlat_t;
     294} ahci_pcireg_mlat_t;
    295295
    296296/*----------------------------------------------------------------------------*/
     
    343343                /** Supports 64-bit Addressing. */
    344344                unsigned int s64a : 1;
    345         } __attribute__((packed));
    346         uint32_t u32;
    347 } __attribute__((packed)) ahci_ghc_cap_t;
     345        };
     346        uint32_t u32;
     347} ahci_ghc_cap_t;
    348348
    349349/** AHCI Memory register Generic Host Control Global Host Control. */
     
    360360                /** AHCI Enable. */
    361361                unsigned int ae : 1;
    362         } __attribute__((packed));
    363         uint32_t u32;
    364 } __attribute__((packed)) ahci_ghc_ghc_t;
     362        };
     363        uint32_t u32;
     364} ahci_ghc_ghc_t;
    365365
    366366/** AHCI Enable mask bit. */
     
    376376         */
    377377        uint32_t u32;
    378 } __attribute__((packed)) ahci_ghc_is_t;
     378} ahci_ghc_is_t;
    379379
    380380/** AHCI Memory register Ports implemented. */
     
    384384         */
    385385        uint32_t u32;
    386 } __attribute__((packed)) ahci_ghc_pi_t;
     386} ahci_ghc_pi_t;
    387387
    388388/** AHCI Memory register AHCI version. */
     
    392392        /** Indicates the major version */
    393393        uint16_t mjr;
    394 } __attribute__((packed)) ahci_ghc_vs_t;
     394} ahci_ghc_vs_t;
    395395
    396396/** AHCI Memory register Command completion coalesce control. */
     
    409409                /** Timeout value in  ms. */
    410410                uint16_t tv;
    411         } __attribute__((packed));
    412         uint32_t u32;
    413 } __attribute__((packed)) ahci_ghc_ccc_ctl_t;
     411        };
     412        uint32_t u32;
     413} ahci_ghc_ccc_ctl_t;
    414414
    415415/** AHCI Memory register Command completion coalescing ports. */
     
    420420         */
    421421        uint32_t u32;
    422 } __attribute__((packed)) ahci_ghc_ccc_ports_t;
     422} ahci_ghc_ccc_ports_t;
    423423
    424424/** AHCI Memory register Enclosure management location. */
     
    431431         */
    432432        uint16_t ofst;
    433 } __attribute__((packed)) ahci_ghc_em_loc;
     433} ahci_ghc_em_loc;
    434434
    435435/** AHCI Memory register Enclosure management control. */
     
    466466                /** Reserved. */
    467467                unsigned int reserved4 : 4;
    468         } __attribute__((packed));
    469         uint32_t u32;
    470 } __attribute__((packed)) ahci_ghc_em_ctl_t;
     468        };
     469        uint32_t u32;
     470} ahci_ghc_em_ctl_t;
    471471
    472472/** AHCI Memory register HBA capatibilities extended. */
     
    483483                /** Reserved. */
    484484                unsigned int reserved : 29;
    485         } __attribute__((packed));
    486         uint32_t u32;
    487 } __attribute__((packed)) ahci_ghc_cap2_t;
     485        };
     486        uint32_t u32;
     487} ahci_ghc_cap2_t;
    488488
    489489/** AHCI Memory register BIOS/OS Handoff control and status. */
     
    502502                /** Reserved. */
    503503                unsigned int reserved : 27;
    504         } __attribute__((packed));
    505         uint32_t u32;
    506 } __attribute__((packed)) ahci_ghc_bohc_t;
     504        };
     505        uint32_t u32;
     506} ahci_ghc_bohc_t;
    507507
    508508/** AHCI Memory register Generic Host Control. */
     
    531531        /** BIOS/OS Handoff Control and Status. */
    532532        uint32_t bohc;
    533 } __attribute__((packed)) ahci_ghc_t;
     533} ahci_ghc_t;
    534534
    535535/** AHCI Memory register Port x Command List Base Address. */
     
    545545                 */
    546546                unsigned int clb : 22;
    547         } __attribute__((packed));
    548         uint32_t u32;
    549 } __attribute__((packed)) ahci_port_clb_t;
     547        };
     548        uint32_t u32;
     549} ahci_port_clb_t;
    550550
    551551/** AHCI Memory register Port x Command List Base Address Upper 32-Bits. */
     
    557557         */
    558558        uint32_t u32;
    559 } __attribute__((packed)) ahci_port_clbu_t;
     559} ahci_port_clbu_t;
    560560
    561561/** AHCI Memory register Port x FIS Base Address. */
     
    563563        struct {
    564564                /** Reserved. */
    565                 uint8_t reserved;
     565                unsigned int reserved : 8;
    566566                /** FIS Base Address (FB) - Indicates the 32-bit base physical address
    567567                 * for received FISes. The structure pointed to by this address range
     
    572572                 */
    573573                unsigned int fb : 24;
    574         } __attribute__((packed));
    575         uint32_t u32;
    576 } __attribute__((packed)) ahci_port_fb_t;
     574        };
     575        uint32_t u32;
     576} ahci_port_fb_t;
    577577
    578578/** AHCI Memory register Port x FIS Base Address Upper 32-Bits. */
     
    583583         */
    584584        uint32_t u32;
    585 } __attribute__((packed)) ahci_port_fbu_t;
     585} ahci_port_fbu_t;
    586586
    587587/** AHCI Memory register Port x Interrupt Status. */
     
    626626                /** Cold Port Detect Status. */
    627627                unsigned int cpds : 1;
    628         } __attribute__((packed));
    629         uint32_t u32;
    630 } __attribute__((packed)) ahci_port_is_t;
     628        };
     629        uint32_t u32;
     630} ahci_port_is_t;
    631631
    632632#define AHCI_PORT_IS_DHRS  (1 << 0)
     
    763763                /** Cold Port Detect Enable. */
    764764                unsigned int cpde : 1;
    765         } __attribute__((packed));
    766         uint32_t u32;
    767 } __attribute__((packed)) ahci_port_ie_t;
     765        };
     766        uint32_t u32;
     767} ahci_port_ie_t;
    768768
    769769/** AHCI Memory register Port x Command and Status. */
     
    826826                 */
    827827                unsigned int icc : 4;
    828         } __attribute__((packed));
    829         uint32_t u32;
    830 } __attribute__((packed)) ahci_port_cmd_t;
     828        };
     829        uint32_t u32;
     830} ahci_port_cmd_t;
    831831
    832832/** AHCI Memory register Port x Task File Data. */
     
    843843                /** Reserved. */
    844844                uint16_t reserved;
    845         } __attribute__((packed));
    846         uint32_t u32;
    847 } __attribute__((packed)) ahci_port_tfd_t;
     845        };
     846        uint32_t u32;
     847} ahci_port_tfd_t;
    848848
    849849/** AHCI Memory register Port x Signature. */
     
    858858                /**  LBA High Register */
    859859                uint8_t lba_hr;
    860         } __attribute__((packed));
    861         uint32_t u32;
    862 } __attribute__((packed)) ahci_port_sig_t;
     860        };
     861        uint32_t u32;
     862} ahci_port_sig_t;
    863863
    864864/** AHCI Memory register Port x Serial ATA Status (SCR0: SStatus). */
     
    873873                /** Reserved. */
    874874                unsigned int reserved : 20;
    875         } __attribute__((packed));
    876         uint32_t u32;
    877 } __attribute__((packed)) ahci_port_ssts_t;
     875        };
     876        uint32_t u32;
     877} ahci_port_ssts_t;
    878878
    879879/** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */
     
    888888                /** Reserved. */
    889889                unsigned int reserved : 20;
    890         } __attribute__((packed));
    891         uint32_t u32;
    892 } __attribute__((packed)) ahci_port_sctl_t;
     890        };
     891        uint32_t u32;
     892} ahci_port_sctl_t;
    893893
    894894/** AHCI Memory register Port x Port x Serial ATA Error (SCR1: SError). */
     
    904904         */
    905905        uint16_t diag;
    906 } __attribute__((packed)) ahci_port_serr_t;
     906} ahci_port_serr_t;
    907907
    908908/** AHCI Memory register Port x Serial ATA Active (SCR3: SActive). */
     
    913913         */
    914914        uint32_t u32;
    915 } __attribute__((packed)) ahci_port_sact_t;
     915} ahci_port_sact_t;
    916916
    917917/** AHCI Memory register Port x Command Issue. */
     
    921921         */
    922922        uint32_t u32;
    923 } __attribute__((packed)) ahci_port_ci_t;
     923} ahci_port_ci_t;
    924924
    925925/** AHCI Memory register Port x Serial ATA Notification
     
    934934        /** Reserved. */
    935935        uint16_t reserved;
    936 } __attribute__((packed)) ahci_port_sntf_t;
     936} ahci_port_sntf_t;
    937937
    938938/** AHCI Memory register Port x FIS-based Switching Control.
     
    958958                /** Reserved. */
    959959                unsigned int reserved2 : 1;
    960         } __attribute__((packed));
    961         uint32_t u32;
    962 } __attribute__((packed)) ahci_port_fbs_t;
     960        };
     961        uint32_t u32;
     962} ahci_port_fbs_t;
    963963
    964964/** AHCI Memory register Port. */
     
    10031003        /** Port x Vendor Specific. */
    10041004        uint32_t pxvs[4];
    1005 } __attribute__((packed)) ahci_port_t;
     1005} ahci_port_t;
    10061006
    10071007/** AHCI Memory Registers. */
     
    10171017        /** Ports. */
    10181018        ahci_port_t ports[32];
    1019 } __attribute__((packed)) ahci_memregs_t;
     1019} ahci_memregs_t;
    10201020
    10211021/** AHCI Command header entry. */
     
    10311031        /** Command Table Descriptor Base Address Upper 32-bits. */
    10321032        uint32_t cmdtableu;
    1033 } __attribute__((packed)) ahci_cmdhdr_t;
     1033} ahci_cmdhdr_t;
    10341034
    10351035/** AHCI Command Physical Region Descriptor entry. */
     
    10471047        /** Interrupt on completion */
    10481048        unsigned int ioc : 1;
    1049 } __attribute__((packed)) ahci_cmd_prdt_t;
     1049} ahci_cmd_prdt_t;
    10501050
    10511051#endif
  • uspace/drv/block/ahci/ahci_sata.h

    ra00d555 r730dce77  
    3939typedef struct {
    4040        /** FIS type - always 0x27. */
    41         uint8_t fis_type;
     41        unsigned int fis_type : 8;
    4242        /** Indicate that FIS is a Command - always 0x80. */
    43         uint8_t c;
     43        unsigned int c : 8;
    4444        /** Command - Identity device - 0xec, Set fetures - 0xef. */
    45         uint8_t command;
     45        unsigned int command : 8;
    4646        /** Features - subcommand for set features - set tranfer mode - 0x03. */
    47         uint8_t features;
     47        unsigned int features : 8;
    4848        /** 0:23 bits of LBA. */
    49         uint32_t lba_lower : 24;
     49        unsigned int lba_lower : 24;
    5050        /** Device. */
    51         uint8_t device;
     51        unsigned int device : 8;
    5252        /** 24:47 bits of LBA. */
    53         uint32_t lba_upper : 24;
     53        unsigned int lba_upper : 24;
    5454        /** Features - subcommand for set features - set tranfer mode - 0x03. */
    55         uint8_t features_upper;
     55        unsigned int features_upper : 8;
    5656        /** Sector count - transfer mode for set transfer mode operation. */
    57         uint16_t count;
    58         /** Reserved. */
    59         uint8_t reserved1;
     57        unsigned int count : 16;
     58        /** Reserved. */
     59        unsigned int reserved1 : 8;
    6060        /** Control. */
    61         uint8_t control;
    62         /** Reserved. */
    63         uint32_t reserved2;
    64 } __attribute__((packed)) std_command_frame_t;
     61        unsigned int control : 8;
     62        /** Reserved. */
     63        unsigned int reserved2 : 32;
     64} std_command_frame_t;
    6565
    6666/** Command frame for NCQ data operation. */
     
    105105        /** Reserved. */
    106106        uint8_t reserved6;
    107 } __attribute__((packed)) ncq_command_frame_t;
     107} ncq_command_frame_t;
    108108
    109109/** Data returned from identify device and identify packet device command. */
     
    187187        uint16_t _vs128[1 + 159 - 128];
    188188        uint16_t reserved160[1 + 255 - 160];
    189 } __attribute__((packed)) identify_data_t;
     189} identify_data_t;
    190190
    191191/** Capability bits for register device. */
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