Changeset 7bf9217 in mainline for boot/arch/arm32/src/mm.c
- Timestamp:
- 2013-08-08T20:59:02Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- e93bb24
- Parents:
- 15187c3
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/arm32/src/mm.c
r15187c3 r7bf9217 147 147 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h) 148 148 */ 149 //TODO: Use write-back write-allocate caches 150 pte->tex = section_cacheable(frame) ? 6 : 0; 151 pte->bufferable = section_cacheable(frame) ? 0 : 0; 152 pte->cacheable = section_cacheable(frame) ? 1 : 0; 149 pte->tex = section_cacheable(frame) ? 5 : 0; 150 pte->cacheable = section_cacheable(frame) ? 0 : 0; 151 pte->bufferable = section_cacheable(frame) ? 1 : 0; 153 152 #else 154 153 pte->bufferable = 1; … … 184 183 */ 185 184 uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK; 186 val |= TTBR_RGN_W T_CACHE | TTBR_C_FLAG;185 val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG; 187 186 TTBR0_write(val); 188 187 }
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