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Changeset e93bb24 in mainline


Ignore:
Timestamp:
2013-08-15T09:36:14Z (7 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
master
Children:
34847e2
Parents:
7bf9217
Message:

arm32: add details to comments

Location:
boot/arch/arm32/src
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/src/asm.S

    r7bf9217 re93bb24  
    7575        bic     r4, r4, #(1 << CP15_C1_DC)
    7676
    77         #Disable I-cache and Branche predicotrs on non-armv7
     77        # Disable I-cache and Branche predictors.
    7878        bic     r4, r4, #(1 << CP15_C1_IC)
    7979        bic     r4, r4, #(1 << CP15_C1_BP)
     
    8888        dsb
    8989#else
     90        #cp15 dsb, r4 is ignored (should be zero)
    9091        mov r4, #0
    91         #cp15 dsb, r4 is ignored (should be zero)
    9292        mcr p15, 0, r4, c7, c10, 4
    9393#endif
    9494       
    9595        # Clean ICache and BPredictors, r4 ignored (SBZ)
     96        mov r4, #0
    9697        mcr p15, 0, r4, c7, c5, 0
    9798        nop
  • boot/arch/arm32/src/mm.c

    r7bf9217 re93bb24  
    169169         * Create 1:1 virtual-physical mapping.
    170170         * Physical memory on BBxM a BBone starts at 2GB
    171          * boundary, gta02 has a memory mirror at 2GB.
    172          * icp somehow works (probably due to limited address size)
    173          */
    174         for (pfn_t page = 0; page < PTL0_ENTRIES; page++)
     171         * boundary, icp has a memory mirror at 2GB.
     172         * (ARM Integrator Core Module User guide ch. 6.3,  p. 6-7)
     173         * gta02 somehow works (probably due to limited address size),
     174         * s3c2442b manual ch. 5, p.5-1:
     175         * "Address space: 128Mbytes per bank (total 1GB/8 banks)"
     176         */
     177        for (pfn_t page = 0; page < PTL0_ENTRIES; ++page)
    175178                init_ptl0_section(&boot_pt[page], page);
    176179
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