Ignore:
Timestamp:
2014-12-22T17:47:40Z (9 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
8c7d5ad
Parents:
eae91e0 (diff), 759ea0d (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge the CHT pre-integration branch

This branch contains:

  • the merge of lp:~adam-hraska+lp/helenos/rcu, which brings:
  • a new preemptible kernel RCU variant called A-RCU,
  • a preemptible variant of Podzimek's non-preemptible kernel RCU and
  • a new variant of usersace RCU,
  • a new concurrent hash table (CHT) implementation based on RCU,
  • a deployment of CHT in kernel futex handling,
  • a deployment of the userspace RCU in the implementation of upgradable futexes,

all described in Adam Hraska's master thesis named Read-Copy-Update
for HelenOS, defended in 2013 at MFF UK; furthemore, the branch
fixes two synchronization bugs in condvars and waitq, respectively:

  • revid:adam.hraska+hos@gmail.com-20121116144921-3to9u1tn1sg07rg7
  • revid:adam.hraska+hos@gmail.com-20121116173623-km7gwtqixwudpe66
  • build fixes required to pass make check
  • overhaul of ia64 and sparc64 trap handling, to allow exc_dispatch() to be used now when the kernel is more picky about CPU state accounting
  • an important fix of the sparc64/sun4v preemptible trap handler
  • various other fixes of issues discovered on non-x86 architectures
File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/src/trap/sun4u/trap_table.S

    reae91e0 r235d31d  
    6363instruction_access_exception_tl0:
    6464        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    65         PREEMPTIBLE_HANDLER instruction_access_exception
     65        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     66        clr %g5
     67        PREEMPTIBLE_HANDLER exc_dispatch
    6668
    6769/* TT = 0x0a, TL = 0, instruction_access_error */
    … …  
    6971.global instruction_access_error_tl0
    7072instruction_access_error_tl0:
    71         PREEMPTIBLE_HANDLER instruction_access_error
     73        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     74        clr %g5
     75        PREEMPTIBLE_HANDLER exc_dispatch
    7276
    7377/* TT = 0x10, TL = 0, illegal_instruction */
    … …  
    7579.global illegal_instruction_tl0
    7680illegal_instruction_tl0:
    77         PREEMPTIBLE_HANDLER illegal_instruction
     81        mov TT_ILLEGAL_INSTRUCTION, %g2
     82        clr %g5
     83        PREEMPTIBLE_HANDLER exc_dispatch
    7884
    7985/* TT = 0x11, TL = 0, privileged_opcode */
    … …  
    8187.global privileged_opcode_tl0
    8288privileged_opcode_tl0:
    83         PREEMPTIBLE_HANDLER privileged_opcode
     89        mov TT_PRIVILEGED_OPCODE, %g2
     90        clr %g5
     91        PREEMPTIBLE_HANDLER exc_dispatch
    8492
    8593/* TT = 0x12, TL = 0, unimplemented_LDD */
    … …  
    8795.global unimplemented_LDD_tl0
    8896unimplemented_LDD_tl0:
    89         PREEMPTIBLE_HANDLER unimplemented_LDD
     97        mov TT_UNIMPLEMENTED_LDD, %g2
     98        clr %g5
     99        PREEMPTIBLE_HANDLER exc_dispatch
    90100
    91101/* TT = 0x13, TL = 0, unimplemented_STD */
    … …  
    93103.global unimplemented_STD_tl0
    94104unimplemented_STD_tl0:
    95         PREEMPTIBLE_HANDLER unimplemented_STD
     105        mov TT_UNIMPLEMENTED_STD, %g2
     106        clr %g5
     107        PREEMPTIBLE_HANDLER exc_dispatch
    96108
    97109/* TT = 0x20, TL = 0, fb_disabled handler */
    … …  
    99111.global fb_disabled_tl0
    100112fp_disabled_tl0:
    101         PREEMPTIBLE_HANDLER fp_disabled
     113        mov TT_FP_DISABLED, %g2
     114        clr %g5
     115        PREEMPTIBLE_HANDLER exc_dispatch
    102116
    103117/* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
    … …  
    105119.global fb_exception_ieee_754_tl0
    106120fp_exception_ieee_754_tl0:
    107         PREEMPTIBLE_HANDLER fp_exception_ieee_754
     121        mov TT_FP_EXCEPTION_IEEE_754, %g2
     122        clr %g5
     123        PREEMPTIBLE_HANDLER exc_dispatch
    108124
    109125/* TT = 0x22, TL = 0, fb_exception_other handler */
    … …  
    111127.global fb_exception_other_tl0
    112128fp_exception_other_tl0:
    113         PREEMPTIBLE_HANDLER fp_exception_other
     129        mov TT_FP_EXCEPTION_OTHER, %g2
     130        clr %g5
     131        PREEMPTIBLE_HANDLER exc_dispatch
    114132
    115133/* TT = 0x23, TL = 0, tag_overflow */
    … …  
    117135.global tag_overflow_tl0
    118136tag_overflow_tl0:
    119         PREEMPTIBLE_HANDLER tag_overflow
     137        mov TT_TAG_OVERFLOW, %g2
     138        clr %g5
     139        PREEMPTIBLE_HANDLER exc_dispatch
    120140
    121141/* TT = 0x24, TL = 0, clean_window handler */
    … …  
    129149.global division_by_zero_tl0
    130150division_by_zero_tl0:
    131         PREEMPTIBLE_HANDLER division_by_zero
     151        mov TT_DIVISION_BY_ZERO, %g2
     152        clr %g5
     153        PREEMPTIBLE_HANDLER exc_dispatch
    132154
    133155/* TT = 0x30, TL = 0, data_access_exception */
    … …  
    136158data_access_exception_tl0:
    137159        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    138         PREEMPTIBLE_HANDLER data_access_exception
     160        mov TT_DATA_ACCESS_EXCEPTION, %g2
     161        clr %g5
     162        PREEMPTIBLE_HANDLER exc_dispatch
    139163
    140164/* TT = 0x32, TL = 0, data_access_error */
    … …  
    142166.global data_access_error_tl0
    143167data_access_error_tl0:
    144         PREEMPTIBLE_HANDLER data_access_error
     168        mov TT_DATA_ACCESS_ERROR, %g2
     169        clr %g5
     170        PREEMPTIBLE_HANDLER exc_dispatch
    145171
    146172/* TT = 0x34, TL = 0, mem_address_not_aligned */
    … …  
    148174.global mem_address_not_aligned_tl0
    149175mem_address_not_aligned_tl0:
    150         PREEMPTIBLE_HANDLER mem_address_not_aligned
     176        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     177        clr %g5
     178        PREEMPTIBLE_HANDLER exc_dispatch
    151179
    152180/* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
    … …  
    154182.global LDDF_mem_address_not_aligned_tl0
    155183LDDF_mem_address_not_aligned_tl0:
    156         PREEMPTIBLE_HANDLER LDDF_mem_address_not_aligned
     184        mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     185        clr %g5
     186        PREEMPTIBLE_HANDLER exc_dispatch
    157187
    158188/* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
    … …  
    160190.global STDF_mem_address_not_aligned_tl0
    161191STDF_mem_address_not_aligned_tl0:
    162         PREEMPTIBLE_HANDLER STDF_mem_address_not_aligned
     192        mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
     193        clr %g5
     194        PREEMPTIBLE_HANDLER exc_dispatch
    163195
    164196/* TT = 0x37, TL = 0, privileged_action */
    … …  
    166198.global privileged_action_tl0
    167199privileged_action_tl0:
    168         PREEMPTIBLE_HANDLER privileged_action
     200        mov TT_PRIVILEGED_ACTION, %g2
     201        clr %g5
     202        PREEMPTIBLE_HANDLER exc_dispatch
    169203
    170204/* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
    … …  
    172206.global LDQF_mem_address_not_aligned_tl0
    173207LDQF_mem_address_not_aligned_tl0:
    174         PREEMPTIBLE_HANDLER LDQF_mem_address_not_aligned
     208        mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     209        clr %g5
     210        PREEMPTIBLE_HANDLER exc_dispatch
    175211
    176212/* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
    … …  
    178214.global STQF_mem_address_not_aligned_tl0
    179215STQF_mem_address_not_aligned_tl0:
    180         PREEMPTIBLE_HANDLER STQF_mem_address_not_aligned
     216        mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
     217        clr %g5
     218        PREEMPTIBLE_HANDLER exc_dispatch
    181219
    182220/* TT = 0x41, TL = 0, interrupt_level_1 handler */
    … …  
    184222.global interrupt_level_1_handler_tl0
    185223interrupt_level_1_handler_tl0:
    186         INTERRUPT_LEVEL_N_HANDLER 1
     224        mov TT_INTERRUPT_LEVEL_1, %g2
     225        clr %g5
     226        PREEMPTIBLE_HANDLER exc_dispatch
    187227
    188228/* TT = 0x42, TL = 0, interrupt_level_2 handler */
    … …  
    190230.global interrupt_level_2_handler_tl0
    191231interrupt_level_2_handler_tl0:
    192         INTERRUPT_LEVEL_N_HANDLER 2
     232        mov TT_INTERRUPT_LEVEL_2, %g2
     233        clr %g5
     234        PREEMPTIBLE_HANDLER exc_dispatch
    193235
    194236/* TT = 0x43, TL = 0, interrupt_level_3 handler */
    … …  
    196238.global interrupt_level_3_handler_tl0
    197239interrupt_level_3_handler_tl0:
    198         INTERRUPT_LEVEL_N_HANDLER 3
     240        mov TT_INTERRUPT_LEVEL_3, %g2
     241        clr %g5
     242        PREEMPTIBLE_HANDLER exc_dispatch
    199243
    200244/* TT = 0x44, TL = 0, interrupt_level_4 handler */
    … …  
    202246.global interrupt_level_4_handler_tl0
    203247interrupt_level_4_handler_tl0:
    204         INTERRUPT_LEVEL_N_HANDLER 4
     248        mov TT_INTERRUPT_LEVEL_4, %g2
     249        clr %g5
     250        PREEMPTIBLE_HANDLER exc_dispatch
    205251
    206252/* TT = 0x45, TL = 0, interrupt_level_5 handler */
    … …  
    208254.global interrupt_level_5_handler_tl0
    209255interrupt_level_5_handler_tl0:
    210         INTERRUPT_LEVEL_N_HANDLER 5
     256        mov TT_INTERRUPT_LEVEL_5, %g2
     257        clr %g5
     258        PREEMPTIBLE_HANDLER exc_dispatch
    211259
    212260/* TT = 0x46, TL = 0, interrupt_level_6 handler */
    … …  
    214262.global interrupt_level_6_handler_tl0
    215263interrupt_level_6_handler_tl0:
    216         INTERRUPT_LEVEL_N_HANDLER 6
     264        mov TT_INTERRUPT_LEVEL_6, %g2
     265        clr %g5
     266        PREEMPTIBLE_HANDLER exc_dispatch
    217267
    218268/* TT = 0x47, TL = 0, interrupt_level_7 handler */
    … …  
    220270.global interrupt_level_7_handler_tl0
    221271interrupt_level_7_handler_tl0:
    222         INTERRUPT_LEVEL_N_HANDLER 7
     272        mov TT_INTERRUPT_LEVEL_7, %g2
     273        clr %g5
     274        PREEMPTIBLE_HANDLER exc_dispatch
    223275
    224276/* TT = 0x48, TL = 0, interrupt_level_8 handler */
    … …  
    226278.global interrupt_level_8_handler_tl0
    227279interrupt_level_8_handler_tl0:
    228         INTERRUPT_LEVEL_N_HANDLER 8
     280        mov TT_INTERRUPT_LEVEL_8, %g2
     281        clr %g5
     282        PREEMPTIBLE_HANDLER exc_dispatch
    229283
    230284/* TT = 0x49, TL = 0, interrupt_level_9 handler */
    … …  
    232286.global interrupt_level_9_handler_tl0
    233287interrupt_level_9_handler_tl0:
    234         INTERRUPT_LEVEL_N_HANDLER 9
     288        mov TT_INTERRUPT_LEVEL_9, %g2
     289        clr %g5
     290        PREEMPTIBLE_HANDLER exc_dispatch
    235291
    236292/* TT = 0x4a, TL = 0, interrupt_level_10 handler */
    … …  
    238294.global interrupt_level_10_handler_tl0
    239295interrupt_level_10_handler_tl0:
    240         INTERRUPT_LEVEL_N_HANDLER 10
     296        mov TT_INTERRUPT_LEVEL_10, %g2
     297        clr %g5
     298        PREEMPTIBLE_HANDLER exc_dispatch
    241299
    242300/* TT = 0x4b, TL = 0, interrupt_level_11 handler */
    … …  
    244302.global interrupt_level_11_handler_tl0
    245303interrupt_level_11_handler_tl0:
    246         INTERRUPT_LEVEL_N_HANDLER 11
     304        mov TT_INTERRUPT_LEVEL_11, %g2
     305        clr %g5
     306        PREEMPTIBLE_HANDLER exc_dispatch
    247307
    248308/* TT = 0x4c, TL = 0, interrupt_level_12 handler */
    … …  
    250310.global interrupt_level_12_handler_tl0
    251311interrupt_level_12_handler_tl0:
    252         INTERRUPT_LEVEL_N_HANDLER 12
     312        mov TT_INTERRUPT_LEVEL_12, %g2
     313        clr %g5
     314        PREEMPTIBLE_HANDLER exc_dispatch
    253315
    254316/* TT = 0x4d, TL = 0, interrupt_level_13 handler */
    … …  
    256318.global interrupt_level_13_handler_tl0
    257319interrupt_level_13_handler_tl0:
    258         INTERRUPT_LEVEL_N_HANDLER 13
     320        mov TT_INTERRUPT_LEVEL_13, %g2
     321        clr %g5
     322        PREEMPTIBLE_HANDLER exc_dispatch
    259323
    260324/* TT = 0x4e, TL = 0, interrupt_level_14 handler */
    … …  
    262326.global interrupt_level_14_handler_tl0
    263327interrupt_level_14_handler_tl0:
    264         INTERRUPT_LEVEL_N_HANDLER 14
     328        mov TT_INTERRUPT_LEVEL_14, %g2
     329        clr %g5
     330        PREEMPTIBLE_HANDLER exc_dispatch
    265331
    266332/* TT = 0x4f, TL = 0, interrupt_level_15 handler */
    … …  
    268334.global interrupt_level_15_handler_tl0
    269335interrupt_level_15_handler_tl0:
    270         INTERRUPT_LEVEL_N_HANDLER 15
     336        mov TT_INTERRUPT_LEVEL_15, %g2
     337        clr %g5
     338        PREEMPTIBLE_HANDLER exc_dispatch
    271339
    272340/* TT = 0x60, TL = 0, interrupt_vector_trap handler */
    … …  
    274342.global interrupt_vector_trap_handler_tl0
    275343interrupt_vector_trap_handler_tl0:
    276         INTERRUPT_VECTOR_TRAP_HANDLER
     344        mov TT_INTERRUPT_VECTOR_TRAP, %g2
     345        clr %g5
     346        PREEMPTIBLE_HANDLER exc_dispatch
    277347
    278348/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
    … …  
    342412.global trap_instruction_\cur\()_tl0
    343413trap_instruction_\cur\()_tl0:
     414        mov \cur, %g2
    344415        ba %xcc, trap_instruction_handler
    345         mov \cur, %g2
     416        clr %g5
    346417.endr
    347418
    … …  
    356427        wrpr %g0, 1, %tl
    357428        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    358         PREEMPTIBLE_HANDLER instruction_access_exception
     429        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
     430        clr %g5
     431        PREEMPTIBLE_HANDLER exc_dispatch
    359432
    360433/* TT = 0x0a, TL > 0, instruction_access_error */
    … …  
    363436instruction_access_error_tl1:
    364437        wrpr %g0, 1, %tl
    365         PREEMPTIBLE_HANDLER instruction_access_error
     438        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
     439        clr %g5
     440        PREEMPTIBLE_HANDLER exc_dispatch
    366441
    367442/* TT = 0x10, TL > 0, illegal_instruction */
    … …  
    370445illegal_instruction_tl1:
    371446        wrpr %g0, 1, %tl
    372         PREEMPTIBLE_HANDLER illegal_instruction
     447        mov TT_ILLEGAL_INSTRUCTION, %g2
     448        clr %g5
     449        PREEMPTIBLE_HANDLER exc_dispatch
    373450
    374451/* TT = 0x24, TL > 0, clean_window handler */
    … …  
    383460division_by_zero_tl1:
    384461        wrpr %g0, 1, %tl
    385         PREEMPTIBLE_HANDLER division_by_zero
     462        mov TT_DIVISION_BY_ZERO, %g2
     463        clr %g5
     464        PREEMPTIBLE_HANDLER exc_dispatch
    386465
    387466/* TT = 0x30, TL > 0, data_access_exception */
    … …  
    391470        wrpr %g0, 1, %tl
    392471        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    393         PREEMPTIBLE_HANDLER data_access_exception
     472        mov TT_DATA_ACCESS_EXCEPTION, %g2
     473        clr %g5
     474        PREEMPTIBLE_HANDLER exc_dispatch
    394475
    395476/* TT = 0x32, TL > 0, data_access_error */
    … …  
    398479data_access_error_tl1:
    399480        wrpr %g0, 1, %tl
    400         PREEMPTIBLE_HANDLER data_access_error
     481        mov TT_DATA_ACCESS_ERROR, %g2
     482        clr %g5
     483        PREEMPTIBLE_HANDLER exc_dispatch
    401484
    402485/* TT = 0x34, TL > 0, mem_address_not_aligned */
    … …  
    405488mem_address_not_aligned_tl1:
    406489        wrpr %g0, 1, %tl
    407         PREEMPTIBLE_HANDLER mem_address_not_aligned
     490        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
     491        clr %g5
     492        PREEMPTIBLE_HANDLER exc_dispatch
    408493
    409494/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
    … …  
    470555 *      %g1             Address of function to call if this is not a syscall.
    471556 *      %g2             First argument for the function.
     557 *      %g5             I/DTLB_TAG_ACCESS register if applicable.
    472558 *      %g6             Pre-set as kernel stack base if trap from userspace.
    473559 *      %g7             Pre-set as address of the userspace window buffer.
    474560 */
    475561.macro PREEMPTIBLE_HANDLER_TEMPLATE is_syscall
    476         /*
    477          * ASSERT(%tl == 1)
    478          */
    479         rdpr %tl, %g3
    480         cmp %g3, 1
    481         be %xcc, 1f
    482         nop
    483         ! this is for debugging, if we ever get here it will be easy to find
    484 0:      ba,a %xcc, 0b
    485 
    486 1:
    487562.if NOT(\is_syscall)
    488563        rdpr %tstate, %g3
    … …  
    502577        bnz %xcc, 0f                            ! ...skip setting of kernel stack and primary context
    503578        nop
    504        
    505579.endif
     580
    506581        /*
    507582         * Normal window spills will go to the userspace window buffer.
    … …  
    516591         * and the new window's %fp.
    517592         */
    518         save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     593        save %g6, -ISTATE_SIZE, %sp
    519594
    520595.if \is_syscall
    … …  
    548623        ba,a %xcc, 1f
    5496240:
    550         save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     625        save %sp, -ISTATE_SIZE, %sp
    551626
    552627        /*
    … …  
    570645.else
    571646        ! store the syscall number on the stack as 7th argument
    572         stx %g2, [%sp + STACK_WINDOW_SAVE_AREA_SIZE + STACK_BIAS + STACK_ARG6]
     647        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
    573648.endif
    574649
    575650        /*
    576          * Save TSTATE, TPC and TNPC aside.
     651         * Save TSTATE, TPC, TNPC and I/DTLB_TAG_ACCESS aside.
    577652         */
    578653        rdpr %tstate, %g1
    … …  
    581656        rd %y, %g4
    582657
    583         stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
    584         stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
    585         stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
     658        stx %g1, [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE]
     659        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_TPC]
     660        stx %g3, [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC]
     661        stx %g5, [%sp + STACK_BIAS + ISTATE_OFFSET_TLB_TAG_ACCESS]
    586662
    587663        /*
    588664         * Save the Y register.
    589          * This register is deprecated according to SPARC V9 specification
    590          * and is only present for backward compatibility with previous
    591          * versions of the SPARC architecture.
    592          * Surprisingly, gcc makes use of this register without a notice.
    593          */
    594         stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
     665         */
     666        stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y]
    595667       
    596668        wrpr %g0, 0, %tl
    … …  
    603675         */
    604676        call %l0
    605         add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
     677        add %sp, STACK_BIAS, %o1
    606678.else
    607679        /*
    … …  
    621693         * Read TSTATE, TPC and TNPC from saved copy.
    622694         */
    623         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
    624         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
    625         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
     695        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE], %g1
     696        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TPC], %g2
     697        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC], %g3
    626698
    627699        /*
    … …  
    644716         * Restore Y.
    645717         */
    646         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4
     718        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_Y], %g4
    647719        wr %g4, %y
    648720
    … …  
    684756         */
    685757        mov %sp, %g2
    686         stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
    687         stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
    688         stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
    689         stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
    690         stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
    691         stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
    692         stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
    693         stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
     758        stx %i0, [%sp + STACK_BIAS + ISTATE_OFFSET_O0]
     759        stx %i1, [%sp + STACK_BIAS + ISTATE_OFFSET_O1]
     760        stx %i2, [%sp + STACK_BIAS + ISTATE_OFFSET_O2]
     761        stx %i3, [%sp + STACK_BIAS + ISTATE_OFFSET_O3]
     762        stx %i4, [%sp + STACK_BIAS + ISTATE_OFFSET_O4]
     763        stx %i5, [%sp + STACK_BIAS + ISTATE_OFFSET_O5]
     764        stx %i6, [%sp + STACK_BIAS + ISTATE_OFFSET_O6]
     765        stx %i7, [%sp + STACK_BIAS + ISTATE_OFFSET_O7]
    694766        wrpr %l0, 0, %cwp
    695767        mov %g2, %sp
    696         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
    697         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
    698         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
    699         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
    700         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
    701         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
    702         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
    703         ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
     768        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O0], %i0
     769        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O1], %i1
     770        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O2], %i2
     771        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O3], %i3
     772        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O4], %i4
     773        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O5], %i5
     774        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O6], %i6
     775        ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O7], %i7
    704776
    705777        /*
    … …  
    807879         * If the:
    808880         *
    809          *      save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     881         *      save %g6, -ISTATE_SIZE, %sp
    810882         *
    811883         * instruction trapped and spilled a register window into the userspace
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