Changeset 0c40fd5 in mainline for kernel/arch/arm32/include/arch/mm/page.h

Timestamp:

2013-08-07T18:38:44Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ae5fb7c8

Parents:

8ff767b

Message:

arm32: Fix pagetables in cacheable memory.

Set memory attributes in TTBR0/1

File:

• kernel/arch/arm32/include/arch/mm/page.h (modified) (1 diff)

kernel/arch/arm32/include/arch/mm/page.h

@@ -145 +145 @@
  * @param pt Pointer to the page table to set.
  *
+ * Page tables are always in cacheable memory.
+ * Make sure the memory type is correct.
  */
 NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
 {
-        TTBR0_write((uint32_t)pt);
+        uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
+        val |= TTBR_RGN_WT_CACHE | TTBR_C_FLAG;
+        TTBR0_write(val);
 }