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Changeset 0c40fd5 in mainline


Ignore:
Timestamp:
2013-08-07T18:38:44Z (7 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
master
Children:
ae5fb7c8
Parents:
8ff767b
Message:

arm32: Fix pagetables in cacheable memory.

Set memory attributes in TTBR0/1

Location:
kernel/arch/arm32/include/arch
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/arch/cp15.h

    r8ff767b r0c40fd5  
    301301
    302302/* Memory protection and control registers */
     303enum {
     304        TTBR_ADDR_MASK = 0xffffff80,
     305        TTBR_NOS_FLAG = 1 << 5,
     306        TTBR_RGN_MASK = 0x3 << 3,
     307        TTBR_RGN_NO_CACHE = 0x0 << 3,
     308        TTBR_RGN_WBWA_CACHE = 0x1 << 3,
     309        TTBR_RGN_WT_CACHE = 0x2 << 3,
     310        TTBR_RGN_WB_CACHE = 0x3 << 3,
     311        TTBR_S_FLAG = 1 << 1,
     312        TTBR_C_FLAG = 1 << 0,
     313};
    303314CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
    304315CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
  • kernel/arch/arm32/include/arch/mm/page.h

    r8ff767b r0c40fd5  
    145145 * @param pt Pointer to the page table to set.
    146146 *
     147 * Page tables are always in cacheable memory.
     148 * Make sure the memory type is correct.
    147149 */
    148150NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    149151{
    150         TTBR0_write((uint32_t)pt);
     152        uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
     153        val |= TTBR_RGN_WT_CACHE | TTBR_C_FLAG;
     154        TTBR0_write(val);
    151155}
    152156
  • kernel/arch/arm32/include/arch/mm/page_armv4.h

    r8ff767b r0c40fd5  
    120120#define PTE_DESCRIPTOR_SMALL_PAGE       2
    121121
    122 #define pt_coherence_m(page, count)
     122#define pt_coherence_m(pt, count) \
     123do { \
     124        for (unsigned i = 0; i < count; ++i) \
     125                DCCMVAU_write((uintptr_t)(pt + i)); \
     126        read_barrier(); \
     127} while (0)
    123128
    124129/** Returns level 0 page table entry flags.
  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    r8ff767b r0c40fd5  
    151151 *
    152152 * ARM Architecture reference chp. B3.10.1 p. B3-1375
    153  */
    154 //TODO: DCCMVAU does not work.
     153 * @note: see TTRB0/1 for pt memory type
     154 */
    155155#define pt_coherence_m(pt, count) \
    156156do { \
    157157        for (unsigned i = 0; i < count; ++i) \
    158                 DCCMVAC_write((uintptr_t)(pt + i)); \
     158                DCCMVAU_write((uintptr_t)(pt + i)); \
    159159        read_barrier(); \
    160160} while (0)
     
    300300        p->should_be_zero_0 = 0;
    301301        p->should_be_zero_1 = 0;
    302         write_barrier();
    303302        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
    304303        pt_coherence(p);
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