Changeset b3f967c in mainline for kernel/arch/arm32/include/arch/mm/page.h
- Timestamp:
- 2013-08-06T23:06:38Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- bb75646
- Parents:
- e40b8066
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/include/arch/mm/page.h
re40b8066 rb3f967c 41 41 #include <arch/exception.h> 42 42 #include <arch/barrier.h> 43 #include <arch/cp15.h> 43 44 #include <trace.h> 44 45 … … 129 130 set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) 130 131 132 133 #define pt_coherence(page) pt_coherence_m(page, 1) 134 131 135 #if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a) 132 136 #include "page_armv6.h" … … 137 141 #endif 138 142 143 /** Sets the address of level 0 page table. 144 * 145 * @param pt Pointer to the page table to set. 146 * 147 */ 148 NO_TRACE static inline void set_ptl0_addr(pte_t *pt) 149 { 150 TTBR0_write((uint32_t)pt); 151 } 152 153 NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address) 154 { 155 pt[i].l0.coarse_table_addr = address >> 10; 156 pt_coherence(&pt[i].l0); 157 } 158 159 NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address) 160 { 161 pt[i].l1.frame_base_addr = address >> 12; 162 pt_coherence(&pt[i].l1); 163 } 164 139 165 #endif 140 166
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