Changeset e2cc9a0 in mainline for kernel/genarch/src/ofw/ebus.c
- Timestamp:
- 2006-10-06T22:37:15Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 33b1903
- Parents:
- 233af8c5
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/genarch/src/ofw/ebus.c
r233af8c5 re2cc9a0 37 37 38 38 #include <genarch/ofw/ofw_tree.h> 39 #include <arch/drivers/pci.h> 39 40 #include <arch/memstr.h> 41 #include <arch/trap/interrupt.h> 40 42 #include <func.h> 41 43 #include <panic.h> … … 43 45 #include <macros.h> 44 46 47 /** Apply EBUS ranges to EBUS register. */ 45 48 bool ofw_ebus_apply_ranges(ofw_tree_node_t *node, ofw_ebus_reg_t *reg, uintptr_t *pa) 46 49 { … … 113 116 * We found the device that functions as an interrupt controller 114 117 * for the interrupt. We also found mapping from interrupt to INR. 118 * What needs to be done now is to verify that this indeed is a PCI 119 * node. 115 120 */ 116 121 117 122 controller = ofw_tree_find_node_by_handle(ofw_tree_lookup("/"), intr_map[i].controller_handle); 123 if (!controller) 124 return false; 125 126 if (strcmp(ofw_tree_node_name(controller), "pci") != 0) { 127 /* 128 * This is not a PCI node. 129 */ 130 return false; 131 } 132 133 pci_t *pci = controller->device; 134 if (!pci) { 135 pci = pci_init(controller); 136 if (!pci) 137 return false; 138 controller->device = pci; 139 140 } 141 pci_enable_interrupt(pci, intr_map[i].controller_inr); 142 143 *inr = intr_map[i].controller_inr; 144 *inr |= 0x1f << IGN_SHIFT; /* 0x1f is hardwired IGN */ 118 145 119 *inr = intr_map[i].controller_inr;120 146 return true; 121 147 }
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