Changeset e25eca80 in mainline for kernel/arch/sparc64

Timestamp:

2008-06-13T20:36:38Z (17 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

d5087aa

Parents:

80dabb8d

Message:

Add smc_coherence() macro to all architectures.
So far, only amd64, ia32, ia64 and sparc64 are implemented.

Location:

kernel/arch/sparc64

Files:

• include/barrier.h (modified) (2 diffs)
• include/mm/cache_spec.h (added)
• include/mm/tlb.h (modified) (7 diffs)
• src/mm/cache.S (modified) (1 diff)

kernel/arch/sparc64/include/barrier.h

@@ -58 +58 @@
         asm volatile ("membar #StoreStore\n" ::: "memory")
 
+static inline void flush(uintptr_t addr)
+{
+        asm volatile ("flush %0\n" :: "r" (addr) : "memory");
+}
+
 /** Flush Instruction Memory instruction. */
-static inline void flush(void)
+static inline void flush_blind(void)
 {
         /*
@@ -80 +85 @@
 }
 
+#define smc_coherence(a)        \
+{                               \
+        write_barrier();        \
+        flush((a));             \
+}
+
 #endif
 

kernel/arch/sparc64/include/mm/tlb.h

@@ -161 +161 @@
 {
         asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
-        flush();
+        flush_blind();
 }
 
@@ -180 +180 @@
 {
         asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
-        flush();
+        flush_blind();
 }
 
@@ -210 +210 @@
         reg.tlb_entry = entry;
         asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
-        flush();
+        flush_blind();
 }
 
@@ -280 +280 @@
 {
         asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
-        flush();
+        flush_blind();
 }
 
@@ -319 +319 @@
 {
         asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
-        flush();
+        flush_blind();
 }
 
@@ -348 +348 @@
 {
         asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
-        flush();
+        flush_blind();
 }
 
@@ -401 +401 @@
                                                          * address within the
                                                          * ASI */ 
-        flush();
+        flush_blind();
 }
 

kernel/arch/sparc64/src/mm/cache.S

@@ -28 +28 @@
 
 #include <arch/arch.h>
-
-#define DCACHE_SIZE             (16 * 1024)
-#define DCACHE_LINE_SIZE        32      
+#include <arch/mm/cache_spec.h>
 
 #define DCACHE_TAG_SHIFT        2