Changeset d5087aa in mainline

Timestamp:

2008-06-14T10:29:58Z (17 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

eeaf667

Parents:

e25eca80

Message:

Add smc_coherence_block().

Location:

kernel/arch

Files:

• arm32/include/barrier.h (modified) (1 diff)
• ia32/include/barrier.h (modified) (1 diff)
• ia64/include/barrier.h (modified) (1 diff)
• mips32/include/barrier.h (modified) (1 diff)
• ppc32/include/barrier.h (modified) (1 diff)
• ppc64/include/barrier.h (modified) (1 diff)
• sparc64/include/barrier.h (modified) (2 diffs)

kernel/arch/arm32/include/barrier.h

@@ -48 +48 @@
 
 #define smc_coherence(a)
+#define smc_coherence_block(a, l)
 
 #endif

kernel/arch/ia32/include/barrier.h

@@ -92 +92 @@
  */
 #define smc_coherence(a)                write_barrier()
+#define smc_coherence_block(a, l)       write_barrier()
 
 #endif

kernel/arch/ia64/include/barrier.h

@@ -63 +63 @@
 }
 
+#define FC_INVAL_MIN            32
+#define smc_coherence_block(a, l)               \
+{                                               \
+        unsigned long i;                        \
+        for (i = 0; i < (l); i += FC_INVAL_MIN) \
+                fc_i((void *)(a) + i);          \
+        sync_i();                               \
+        srlz_i();                               \
+}
+
 #endif
 

kernel/arch/mips32/include/barrier.h

@@ -47 +47 @@
 
 #define smc_coherence(a)
+#define smc_coherence_block(a, l)
 
 #endif

kernel/arch/ppc32/include/barrier.h

@@ -44 +44 @@
 
 #define smc_coherence(a)
+#define smc_coherence_block(a, l)
 
 #endif

kernel/arch/ppc64/include/barrier.h

@@ -44 +44 @@
 
 #define smc_coherence(a)
+#define smc_coherence_block(a, l)
 
 #endif

kernel/arch/sparc64/include/barrier.h

@@ -58 +58 @@
         asm volatile ("membar #StoreStore\n" ::: "memory")
 
-static inline void flush(uintptr_t addr)
-{
-        asm volatile ("flush %0\n" :: "r" (addr) : "memory");
-}
+#define flush(a)                \
+        asm volatile ("flush %0\n" :: "r" ((a)) : "memory")
 
 /** Flush Instruction Memory instruction. */
@@ -91 +89 @@
 }
 
+#define FLUSH_INVAL_MIN         4
+#define smc_coherence_block(a, l)                       \
+{                                                       \
+        unsigned long i;                                \
+        write_barrier();                                \
+        for (i = 0; i < (l); i += FLUSH_INVAL_MIN)      \
+                flush((void *)(a) + i);                 \
+}
+
 #endif