Ignore:
Timestamp:
2008-06-13T20:36:38Z (17 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
d5087aa
Parents:
80dabb8d
Message:

Add smc_coherence() macro to all architectures.
So far, only amd64, ia32, ia64 and sparc64 are implemented.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/barrier.h

    r80dabb8d re25eca80  
    5858        asm volatile ("membar #StoreStore\n" ::: "memory")
    5959
     60static inline void flush(uintptr_t addr)
     61{
     62        asm volatile ("flush %0\n" :: "r" (addr) : "memory");
     63}
     64
    6065/** Flush Instruction Memory instruction. */
    61 static inline void flush(void)
     66static inline void flush_blind(void)
    6267{
    6368        /*
    … …  
    8085}
    8186
     87#define smc_coherence(a)        \
     88{                               \
     89        write_barrier();        \
     90        flush((a));             \
     91}
     92
    8293#endif
    8394
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