- Timestamp:
- 2013-03-28T20:39:16Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 2d1fdcad
- Parents:
- cc3c27ad (diff), 5d9fce4 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - Location:
- kernel
- Files:
-
- 6 added
- 23 edited
-
arch/amd64/src/mm/page.c (modified) (2 diffs)
-
arch/arm32/src/fpu_context.c (modified) (1 diff)
-
arch/ia32/src/mm/page.c (modified) (2 diffs)
-
arch/mips32/Makefile.inc (modified) (3 diffs)
-
arch/mips32/_link.ld.in (modified) (1 diff)
-
arch/mips32/include/arch/arch.h (modified) (2 diffs)
-
arch/mips32/include/arch/cp0.h (modified) (1 diff)
-
arch/mips32/include/arch/mach/malta/malta.h (added)
-
arch/mips32/include/arch/mach/msim/msim.h (added)
-
arch/mips32/include/arch/machine_func.h (added)
-
arch/mips32/include/arch/mm/tlb.h (modified) (2 diffs)
-
arch/mips32/src/exception.c (modified) (1 diff)
-
arch/mips32/src/interrupt.c (modified) (5 diffs)
-
arch/mips32/src/mach/malta/malta.c (added)
-
arch/mips32/src/mach/msim/msim.c (added)
-
arch/mips32/src/machine_func.c (added)
-
arch/mips32/src/mips32.c (modified) (5 diffs)
-
arch/mips32/src/mm/frame.c (modified) (4 diffs)
-
arch/mips32/src/mm/tlb.c (modified) (20 diffs)
-
arch/mips64/src/mips64.c (modified) (3 diffs)
-
arch/mips64/src/mm/frame.c (modified) (1 diff)
-
arch/sparc64/src/mm/sun4u/tlb.c (modified) (2 diffs)
-
generic/include/mm/tlb.h (modified) (1 diff)
-
generic/src/mm/as.c (modified) (7 diffs)
-
generic/src/mm/backend_anon.c (modified) (3 diffs)
-
generic/src/mm/backend_elf.c (modified) (4 diffs)
-
generic/src/mm/backend_phys.c (modified) (3 diffs)
-
generic/src/mm/page.c (modified) (3 diffs)
-
generic/src/sysinfo/sysinfo.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/src/mm/page.c
rcc3c27ad rc6a7b3a 78 78 void page_fault(unsigned int n, istate_t *istate) 79 79 { 80 uintptr_t page= read_cr2();80 uintptr_t badvaddr = read_cr2(); 81 81 82 82 if (istate->error_word & PFERR_CODE_RSVD) … … 92 92 access = PF_ACCESS_READ; 93 93 94 as_page_fault(page, access, istate);94 (void) as_page_fault(badvaddr, access, istate); 95 95 } 96 96 -
kernel/arch/arm32/src/fpu_context.c
rcc3c27ad rc6a7b3a 119 119 * rely on user decision to use CONFIG_FPU. 120 120 */ 121 #ifdef PROCESSOR_ARC _armv7_a121 #ifdef PROCESSOR_ARCH_armv7_a 122 122 const uint32_t cpacr = CPACR_read(); 123 123 /* FPU needs access to coprocessor 10 and 11. 124 * Moreover they need to have same access enabled d*/124 * Moreover they need to have same access enabled */ 125 125 if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) && 126 126 ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) { -
kernel/arch/ia32/src/mm/page.c
rcc3c27ad rc6a7b3a 84 84 void page_fault(unsigned int n __attribute__((unused)), istate_t *istate) 85 85 { 86 uintptr_t page;86 uintptr_t badvaddr; 87 87 pf_access_t access; 88 88 89 page= read_cr2();89 badvaddr = read_cr2(); 90 90 91 91 if (istate->error_word & PFERR_CODE_RSVD) … … 97 97 access = PF_ACCESS_READ; 98 98 99 if (as_page_fault(page, access, istate) == AS_PF_FAULT) { 100 fault_if_from_uspace(istate, "Page fault: %#x.", page); 101 panic_memtrap(istate, access, page, NULL); 102 } 99 (void) as_page_fault(badvaddr, access, istate); 103 100 } 104 101 -
kernel/arch/mips32/Makefile.inc
rcc3c27ad rc6a7b3a 29 29 BFD_ARCH = mips 30 30 BFD = binary 31 GCC_CFLAGS += -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -m ips3 -mabi=3231 GCC_CFLAGS += -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mabi=32 32 32 33 33 BITS = 32 … … 36 36 # 37 37 38 ifeq ($(MACHINE),lgxemul)39 BFD_NAME = elf32-tradlittlemips40 ENDIANESS = LE41 endif42 ifeq ($(MACHINE),bgxemul)43 BFD_NAME = elf32-tradbigmips44 ENDIANESS = BE45 GCC_CFLAGS += -D__BE__46 endif47 38 ifeq ($(MACHINE),msim) 48 39 BFD_NAME = elf32-tradlittlemips 49 40 ENDIANESS = LE 41 GCC_CFLAGS += -march=r4000 42 endif 43 ifeq ($(MACHINE),bmalta) 44 BFD_NAME = elf32-tradbigmips 45 ENDIANESS = BE 46 GCC_CFLAGS += -D__BE__ -march=4kc 47 endif 48 ifeq ($(MACHINE),lmalta) 49 BFD_NAME = elf32-tradlittlemips 50 ENDIANESS = LE 51 GCC_CFLAGS += -march=4kc 50 52 endif 51 53 … … 69 71 arch/$(KARCH)/src/fpu_context.c \ 70 72 arch/$(KARCH)/src/ddi/ddi.c \ 71 arch/$(KARCH)/src/smp/dorder.c \ 72 arch/$(KARCH)/src/smp/smp.c 73 arch/$(KARCH)/src/smp/smp.c \ 74 arch/$(KARCH)/src/machine_func.c 75 76 ifeq ($(MACHINE),msim) 77 ARCH_SOURCES += \ 78 arch/$(KARCH)/src/smp/dorder.c 79 endif 80 81 ifeq ($(MACHINE),$(filter lmalta bmalta,$(MACHINE))) 82 ARCH_SOURCES += arch/$(KARCH)/src/mach/malta/malta.c 83 endif 84 ifeq ($(MACHINE),msim) 85 ARCH_SOURCES += arch/$(KARCH)/src/mach/msim/msim.c 86 endif 87 -
kernel/arch/mips32/_link.ld.in
rcc3c27ad rc6a7b3a 10 10 #define mips mips 11 11 12 #if defined(MACHINE_msim) 12 13 #define KERNEL_LOAD_ADDRESS 0x80100000 14 #endif 15 16 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 17 #define KERNEL_LOAD_ADDRESS 0x80200000 18 #endif 13 19 14 20 OUTPUT_ARCH(mips) -
kernel/arch/mips32/include/arch/arch.h
rcc3c27ad rc6a7b3a 44 44 extern size_t cpu_count; 45 45 46 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 47 extern size_t sdram_size; 48 #endif 49 46 50 typedef struct { 47 51 void *addr; … … 51 55 52 56 typedef struct { 57 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 58 uint32_t sdram_size; 59 #endif 53 60 uint32_t cpumap; 54 61 size_t cnt; -
kernel/arch/mips32/include/arch/cp0.h
rcc3c27ad rc6a7b3a 45 45 #define cp0_status_im_shift 8 46 46 #define cp0_status_im_mask 0xff00 47 48 #define cp0_cause_ip_shift 8 49 #define cp0_cause_ip_mask 0xff00 47 50 48 51 #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) -
kernel/arch/mips32/include/arch/mm/tlb.h
rcc3c27ad rc6a7b3a 41 41 #include <trace.h> 42 42 43 #if defined(PROCESSOR_R4000) 43 44 #define TLB_ENTRY_COUNT 48 45 #define TLB_INDEX_BITS 6 46 #elif defined(PROCESSOR_4Kc) 47 #define TLB_ENTRY_COUNT 16 48 #define TLB_INDEX_BITS 4 49 #else 50 #error Please define TLB_ENTRY_COUNT for the target processor. 51 #endif 44 52 45 #define TLB_WIRED 1 46 #define TLB_KSTACK_WIRED_INDEX 0 53 #define TLB_WIRED 0 47 54 48 55 #define TLB_PAGE_MASK_4K (0x000 << 13) … … 112 119 #ifdef __BE__ 113 120 unsigned p : 1; 114 unsigned : 25;115 unsigned index : 6;121 unsigned : 32 - TLB_INDEX_BITS - 1; 122 unsigned index : TLB_INDEX_BITS; 116 123 #else 117 unsigned index : 6;118 unsigned : 25;124 unsigned index : TLB_INDEX_BITS; 125 unsigned : 32 - TLB_INDEX_BITS - 1; 119 126 unsigned p : 1; 120 127 #endif -
kernel/arch/mips32/src/exception.c
rcc3c27ad rc6a7b3a 165 165 static void interrupt_exception(unsigned int n, istate_t *istate) 166 166 { 167 uint32_t ip; 168 uint32_t im; 169 167 170 /* Decode interrupt number and process the interrupt */ 168 uint32_t cause = (cp0_cause_read() >> 8) & 0xff; 171 ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift; 172 im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift; 169 173 170 174 unsigned int i; 171 175 for (i = 0; i < 8; i++) { 172 if (cause & (1 << i)) { 176 177 /* 178 * The interrupt could only occur if it is unmasked in the 179 * status register. On the other hand, an interrupt can be 180 * apparently pending even if it is masked, so we need to 181 * check both the masked and pending interrupts. 182 */ 183 if (im & ip & (1 << i)) { 173 184 irq_t *irq = irq_dispatch_and_lock(i); 174 185 if (irq) { -
kernel/arch/mips32/src/interrupt.c
rcc3c27ad rc6a7b3a 45 45 #define IRQ_COUNT 8 46 46 #define TIMER_IRQ 7 47 48 #ifdef MACHINE_msim 47 49 #define DORDER_IRQ 5 50 #endif 48 51 49 52 function virtual_timer_fnc = NULL; 50 53 static irq_t timer_irq; 54 55 #ifdef MACHINE_msim 51 56 static irq_t dorder_irq; 57 #endif 52 58 53 59 // TODO: This is SMP unsafe!!! … … 151 157 } 152 158 159 #ifdef MACHINE_msim 153 160 static irq_ownership_t dorder_claim(irq_t *irq) 154 161 { … … 160 167 dorder_ipi_ack(1 << dorder_cpuid()); 161 168 } 169 #endif 162 170 163 171 /* Initialize basic tables for exception dispatching */ … … 176 184 cp0_unmask_int(TIMER_IRQ); 177 185 186 #ifdef MACHINE_msim 178 187 irq_initialize(&dorder_irq); 179 188 dorder_irq.devno = device_assign_devno(); … … 184 193 185 194 cp0_unmask_int(DORDER_IRQ); 195 #endif 186 196 } 187 197 -
kernel/arch/mips32/src/mips32.c
rcc3c27ad rc6a7b3a 41 41 #include <memstr.h> 42 42 #include <userspace.h> 43 #include <console/console.h>44 43 #include <syscall/syscall.h> 45 44 #include <sysinfo/sysinfo.h> 46 45 #include <arch/debug.h> 47 46 #include <arch/debugger.h> 48 #include <arch/drivers/msim.h> 49 #include <genarch/fb/fb.h> 50 #include <genarch/drivers/dsrln/dsrlnin.h> 51 #include <genarch/drivers/dsrln/dsrlnout.h> 52 #include <genarch/srln/srln.h> 47 #include <arch/machine_func.h> 53 48 54 49 /* Size of the code jumping to the exception handler code … … 70 65 71 66 size_t cpu_count = 0; 67 68 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 69 size_t sdram_size = 0; 70 #endif 72 71 73 72 /** Performs mips32-specific initialization before main_bsp() is called. */ … … 88 87 cpu_count++; 89 88 } 89 90 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 91 sdram_size = bootinfo->sdram_size; 92 #endif 93 94 /* Initialize machine_ops pointer. */ 95 machine_ops_init(); 90 96 } 91 97 … … 124 130 { 125 131 interrupt_init(); 126 127 #ifdef CONFIG_FB 128 /* GXemul framebuffer */ 129 fb_properties_t gxemul_prop = { 130 .addr = 0x12000000, 131 .offset = 0, 132 .x = 640, 133 .y = 480, 134 .scan = 1920, 135 .visual = VISUAL_RGB_8_8_8, 136 }; 137 138 outdev_t *fbdev = fb_init(&gxemul_prop); 139 if (fbdev) 140 stdout_wire(fbdev); 141 #endif 142 143 #ifdef CONFIG_MIPS_PRN 144 outdev_t *dsrlndev = dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS); 145 if (dsrlndev) 146 stdout_wire(dsrlndev); 147 #endif 132 133 machine_init(); 134 machine_output_init(); 148 135 } 149 136 … … 158 145 void arch_post_smp_init(void) 159 146 { 160 static const char *platform;161 162 147 /* Set platform name. */ 163 #ifdef MACHINE_msim 164 platform = "msim"; 165 #endif 166 #ifdef MACHINE_bgxemul 167 platform = "gxemul"; 168 #endif 169 #ifdef MACHINE_lgxemul 170 platform = "gxemul"; 171 #endif 172 sysinfo_set_item_data("platform", NULL, (void *) platform, 173 str_size(platform)); 174 175 #ifdef CONFIG_MIPS_KBD 176 /* 177 * Initialize the msim/GXemul keyboard port. Then initialize the serial line 178 * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts. 179 */ 180 dsrlnin_instance_t *dsrlnin_instance 181 = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ); 182 if (dsrlnin_instance) { 183 srln_instance_t *srln_instance = srln_init(); 184 if (srln_instance) { 185 indev_t *sink = stdin_wire(); 186 indev_t *srln = srln_wire(srln_instance, sink); 187 dsrlnin_wire(dsrlnin_instance, srln); 188 cp0_unmask_int(MSIM_KBD_IRQ); 189 } 190 } 191 192 /* 193 * This is the necessary evil until the userspace driver is entirely 194 * self-sufficient. 195 */ 196 sysinfo_set_item_val("kbd", NULL, true); 197 sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ); 198 sysinfo_set_item_val("kbd.address.physical", NULL, 199 PA2KA(MSIM_KBD_ADDRESS)); 200 #endif 148 sysinfo_set_item_data("platform", NULL, 149 (void *) machine_get_platform_name(), 150 str_size(machine_get_platform_name())); 151 152 machine_input_init(); 201 153 } 202 154 -
kernel/arch/mips32/src/mm/frame.c
rcc3c27ad rc6a7b3a 40 40 #include <mm/asid.h> 41 41 #include <config.h> 42 #ifdef MACHINE_msim 42 43 #include <arch/drivers/msim.h> 44 #endif 45 #include <arch/arch.h> 43 46 #include <print.h> 44 47 … … 84 87 return false; 85 88 #endif 86 87 #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul) 88 /* gxemul devices */ 89 if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, 90 0x10000000, MiB2SIZE(256))) 89 90 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 91 if (frame >= (sdram_size >> ZERO_PAGE_WIDTH)) 91 92 return false; 92 93 #endif … … 225 226 if (ZERO_PAGE_VALUE != 0xdeadbeef) 226 227 avail = false; 227 #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)228 else {229 ZERO_PAGE_VALUE_KSEG1(frame) = 0xaabbccdd;230 if (ZERO_PAGE_VALUE_KSEG1(frame) != 0xaabbccdd)231 avail = false;232 }233 #endif234 228 } 235 229 } … … 247 241 /* Blacklist interrupt vector frame */ 248 242 frame_mark_unavailable(0, 1); 243 244 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 245 /* Blacklist memory regions used by YAMON. 246 * 247 * The YAMON User's Manual vaguely says the following physical addresses 248 * are taken by YAMON: 249 * 250 * 0x1000 YAMON functions 251 * 0x5000 YAMON code 252 * 253 * These addresses overlap with the beginning of the SDRAM so we need to 254 * make sure they cannot be allocated. 255 * 256 * The User's Manual unfortunately does not say where does the SDRAM 257 * portion used by YAMON end. 258 * 259 * Looking into the YAMON 02.21 sources, it looks like the first free 260 * address is computed dynamically and depends on the size of the YAMON 261 * image. From the YAMON binary, it appears to be 0xc0d50 or roughly 262 * 772 KiB for that particular version. 263 * 264 * Linux is linked to 1MiB which seems to be a safe bet and a reasonable 265 * upper bound for memory taken by YAMON. We will use it too. 266 */ 267 frame_mark_unavailable(0, 1024 * 1024 / FRAME_SIZE); 268 #endif 249 269 250 270 /* Cleanup */ -
kernel/arch/mips32/src/mm/tlb.c
rcc3c27ad rc6a7b3a 48 48 #include <symtab.h> 49 49 50 static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *); 50 #define PFN_SHIFT 12 51 #define VPN_SHIFT 12 52 #define ADDR2VPN(a) ((a) >> VPN_SHIFT) 53 #define ADDR2VPN2(a) (ADDR2VPN((a)) >> 1) 54 #define VPN2ADDR(vpn) ((vpn) << VPN_SHIFT) 55 #define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1) 56 #define PFN2ADDR(pfn) ((pfn) << PFN_SHIFT) 57 58 #define BANK_SELECT_BIT(a) (((a) >> PAGE_WIDTH) & 1) 59 51 60 52 61 /** Initialize TLB. … … 84 93 { 85 94 entry_lo_t lo; 86 entry_hi_t hi;87 asid_t asid;88 95 uintptr_t badvaddr; 89 96 pte_t *pte; 90 97 91 98 badvaddr = cp0_badvaddr_read(); 92 asid = AS->asid; 93 94 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate); 95 if (pte) { 99 100 pte = page_mapping_find(AS, badvaddr, true); 101 if (pte && pte->p) { 96 102 /* 97 103 * Record access to PTE. … … 99 105 pte->a = 1; 100 106 101 tlb_prepare_entry_hi(&hi, asid, badvaddr);102 107 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, 103 108 pte->cacheable, pte->pfn); … … 106 111 * New entry is to be inserted into TLB 107 112 */ 108 cp0_entry_hi_write(hi.value); 109 if ((badvaddr / PAGE_SIZE) % 2 == 0) { 113 if (BANK_SELECT_BIT(badvaddr) == 0) { 110 114 cp0_entry_lo0_write(lo.value); 111 115 cp0_entry_lo1_write(0); … … 116 120 cp0_pagemask_write(TLB_PAGE_MASK_16K); 117 121 tlbwr(); 118 } 122 return; 123 } 124 125 (void) as_page_fault(badvaddr, PF_ACCESS_READ, istate); 119 126 } 120 127 … … 125 132 void tlb_invalid(istate_t *istate) 126 133 { 134 entry_lo_t lo; 127 135 tlb_index_t index; 128 136 uintptr_t badvaddr; 129 entry_lo_t lo;130 entry_hi_t hi;131 137 pte_t *pte; 132 133 badvaddr = cp0_badvaddr_read();134 138 135 139 /* 136 140 * Locate the faulting entry in TLB. 137 141 */ 138 hi.value = cp0_entry_hi_read();139 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);140 cp0_entry_hi_write(hi.value);141 142 tlbp(); 142 143 index.value = cp0_index_read(); 143 144 145 #if defined(PROCESSOR_4Kc) 146 /* 147 * This can happen on a 4Kc when Status.EXL is 1 and there is a TLB miss. 148 * EXL is 1 when interrupts are disabled. The combination of a TLB miss 149 * and disabled interrupts is possible in copy_to/from_uspace(). 150 */ 151 if (index.p) { 152 tlb_refill(istate); 153 return; 154 } 155 #endif 156 144 157 ASSERT(!index.p); 145 158 146 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate); 147 if (pte) { 159 badvaddr = cp0_badvaddr_read(); 160 161 pte = page_mapping_find(AS, badvaddr, true); 162 if (pte && pte->p) { 148 163 /* 149 164 * Read the faulting TLB entry. … … 162 177 * The entry is to be updated in TLB. 163 178 */ 164 if ( (badvaddr / PAGE_SIZE) % 2== 0)179 if (BANK_SELECT_BIT(badvaddr) == 0) 165 180 cp0_entry_lo0_write(lo.value); 166 181 else 167 182 cp0_entry_lo1_write(lo.value); 168 cp0_pagemask_write(TLB_PAGE_MASK_16K);169 183 tlbwi(); 170 } 184 return; 185 } 186 187 (void) as_page_fault(badvaddr, PF_ACCESS_READ, istate); 171 188 } 172 189 … … 177 194 void tlb_modified(istate_t *istate) 178 195 { 196 entry_lo_t lo; 179 197 tlb_index_t index; 180 198 uintptr_t badvaddr; 181 entry_lo_t lo;182 entry_hi_t hi;183 199 pte_t *pte; 184 200 … … 188 204 * Locate the faulting entry in TLB. 189 205 */ 190 hi.value = cp0_entry_hi_read();191 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);192 cp0_entry_hi_write(hi.value);193 206 tlbp(); 194 207 index.value = cp0_index_read(); 195 208 196 209 /* 197 * Fail if the entry is not in TLB. 210 * Emit warning if the entry is not in TLB. 211 * 212 * We do not assert on this because this could be a manifestation of 213 * an emulator bug, such as QEMU Bug #1128935: 214 * https://bugs.launchpad.net/qemu/+bug/1128935 198 215 */ 199 ASSERT(!index.p); 200 201 pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate); 202 if (pte) { 216 if (index.p) { 217 printf("%s: TLBP failed in exception handler (badvaddr=%#" 218 PRIxn ", ASID=%d).\n", __func__, badvaddr, 219 AS ? AS->asid : -1); 220 return; 221 } 222 223 pte = page_mapping_find(AS, badvaddr, true); 224 if (pte && pte->p && pte->w) { 203 225 /* 204 226 * Read the faulting TLB entry. … … 218 240 * The entry is to be updated in TLB. 219 241 */ 220 if ( (badvaddr / PAGE_SIZE) % 2== 0)242 if (BANK_SELECT_BIT(badvaddr) == 0) 221 243 cp0_entry_lo0_write(lo.value); 222 244 else 223 245 cp0_entry_lo1_write(lo.value); 224 cp0_pagemask_write(TLB_PAGE_MASK_16K);225 246 tlbwi(); 226 } 227 } 228 229 /** Try to find PTE for faulting address. 230 * 231 * @param badvaddr Faulting virtual address. 232 * @param access Access mode that caused the fault. 233 * @param istate Pointer to interrupted state. 234 * 235 * @return PTE on success, NULL otherwise. 236 */ 237 pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate) 238 { 239 entry_hi_t hi; 240 pte_t *pte; 241 242 hi.value = cp0_entry_hi_read(); 243 244 ASSERT(hi.asid == AS->asid); 245 246 /* 247 * Check if the mapping exists in page tables. 248 */ 249 pte = page_mapping_find(AS, badvaddr, true); 250 if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) { 251 /* 252 * Mapping found in page tables. 253 * Immediately succeed. 254 */ 255 return pte; 256 } 257 258 /* 259 * Mapping not found in page tables. 260 * Resort to higher-level page fault handler. 261 */ 262 if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) { 263 pte = page_mapping_find(AS, badvaddr, true); 264 ASSERT(pte && pte->p); 265 ASSERT(pte->w || access != PF_ACCESS_WRITE); 266 return pte; 267 } 268 269 return NULL; 247 return; 248 } 249 250 (void) as_page_fault(badvaddr, PF_ACCESS_WRITE, istate); 270 251 } 271 252 … … 284 265 void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr) 285 266 { 286 hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); 267 hi->value = 0; 268 hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE)); 287 269 hi->asid = asid; 288 270 } … … 291 273 void tlb_print(void) 292 274 { 293 page_mask_t mask ;294 entry_lo_t lo0, lo 1;275 page_mask_t mask, mask_save; 276 entry_lo_t lo0, lo0_save, lo1, lo1_save; 295 277 entry_hi_t hi, hi_save; 296 278 unsigned int i; 297 279 298 280 hi_save.value = cp0_entry_hi_read(); 299 300 printf("[nr] [asid] [vpn2] [mask] [gvdc] [pfn ]\n"); 281 lo0_save.value = cp0_entry_lo0_read(); 282 lo1_save.value = cp0_entry_lo1_read(); 283 mask_save.value = cp0_pagemask_read(); 284 285 printf("[nr] [asid] [vpn2 ] [mask] [gvdc] [pfn ]\n"); 301 286 302 287 for (i = 0; i < TLB_ENTRY_COUNT; i++) { … … 309 294 lo1.value = cp0_entry_lo1_read(); 310 295 311 printf("%-4u %-6u % #6x %#6x %1u%1u%1u%1u %#6x\n",312 i, hi.asid, hi.vpn2, mask.mask,313 lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);314 printf(" %1u%1u%1u%1u %#6x\n",315 lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);296 printf("%-4u %-6u %0#10x %-#6x %1u%1u%1u%1u %0#10x\n", 297 i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask, 298 lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn)); 299 printf(" %1u%1u%1u%1u %0#10x\n", 300 lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn)); 316 301 } 317 302 318 303 cp0_entry_hi_write(hi_save.value); 304 cp0_entry_lo0_write(lo0_save.value); 305 cp0_entry_lo1_write(lo1_save.value); 306 cp0_pagemask_write(mask_save.value); 319 307 } 320 308 … … 322 310 void tlb_invalidate_all(void) 323 311 { 324 ipl_t ipl;325 312 entry_lo_t lo0, lo1; 326 313 entry_hi_t hi_save; 327 314 int i; 328 315 316 ASSERT(interrupts_disabled()); 317 329 318 hi_save.value = cp0_entry_hi_read(); 330 ipl = interrupts_disable();331 319 332 320 for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { … … 346 334 } 347 335 348 interrupts_restore(ipl);349 336 cp0_entry_hi_write(hi_save.value); 350 337 } … … 356 343 void tlb_invalidate_asid(asid_t asid) 357 344 { 358 ipl_t ipl;359 345 entry_lo_t lo0, lo1; 360 346 entry_hi_t hi, hi_save; 361 347 int i; 362 348 349 ASSERT(interrupts_disabled()); 363 350 ASSERT(asid != ASID_INVALID); 364 351 365 352 hi_save.value = cp0_entry_hi_read(); 366 ipl = interrupts_disable();367 353 368 354 for (i = 0; i < TLB_ENTRY_COUNT; i++) { … … 386 372 } 387 373 388 interrupts_restore(ipl);389 374 cp0_entry_hi_write(hi_save.value); 390 375 } … … 400 385 { 401 386 unsigned int i; 402 ipl_t ipl;403 387 entry_lo_t lo0, lo1; 404 388 entry_hi_t hi, hi_save; 405 389 tlb_index_t index; 390 391 ASSERT(interrupts_disabled()); 406 392 407 393 if (asid == ASID_INVALID) … … 409 395 410 396 hi_save.value = cp0_entry_hi_read(); 411 ipl = interrupts_disable();412 397 413 398 for (i = 0; i < cnt + 1; i += 2) { 414 hi.value = 0;415 399 tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); 416 400 cp0_entry_hi_write(hi.value); … … 439 423 } 440 424 441 interrupts_restore(ipl);442 425 cp0_entry_hi_write(hi_save.value); 443 426 } -
kernel/arch/mips64/src/mips64.c
rcc3c27ad rc6a7b3a 46 46 #include <arch/debug.h> 47 47 #include <arch/debugger.h> 48 #ifdef MACHINE_msim 48 49 #include <arch/drivers/msim.h> 50 #endif 49 51 #include <genarch/fb/fb.h> 50 52 #include <genarch/drivers/dsrln/dsrlnin.h> … … 125 127 interrupt_init(); 126 128 127 #ifdef CONFIG_M IPS_PRN129 #ifdef CONFIG_MSIM_PRN 128 130 outdev_t *dsrlndev = dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS); 129 131 if (dsrlndev) … … 151 153 str_size(platform)); 152 154 153 #ifdef CONFIG_MIPS_KBD 154 /* 155 * Initialize the msim/GXemul keyboard port. Then initialize the serial line 156 * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts. 155 #ifdef CONFIG_MSIM_KBD 156 /* 157 * Initialize the msim keyboard port. Then initialize the serial line 158 * module and connect it to the msim keyboard. Enable keyboard 159 * interrupts. 157 160 */ 158 161 dsrlnin_instance_t *dsrlnin_instance -
kernel/arch/mips64/src/mm/frame.c
rcc3c27ad rc6a7b3a 40 40 #include <mm/asid.h> 41 41 #include <config.h> 42 #ifdef MACHINE_msim 42 43 #include <arch/drivers/msim.h> 44 #endif 43 45 #include <print.h> 44 46 -
kernel/arch/sparc64/src/mm/sun4u/tlb.c
rcc3c27ad rc6a7b3a 196 196 void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate) 197 197 { 198 uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE);199 198 size_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; 200 199 pte_t *t; 201 200 202 t = page_mapping_find(AS, page_16k, true);201 t = page_mapping_find(AS, istate->tpc, true); 203 202 if (t && PTE_EXECUTABLE(t)) { 204 203 /* … … 216 215 * handler. 217 216 */ 218 as_page_fault( page_16k, PF_ACCESS_EXEC, istate);217 as_page_fault(istate->tpc, PF_ACCESS_EXEC, istate); 219 218 } 220 219 } -
kernel/generic/include/mm/tlb.h
rcc3c27ad rc6a7b3a 73 73 extern void tlb_shootdown_ipi_recv(void); 74 74 #else 75 #define tlb_shootdown_start(w, x, y, z) (0)76 #define tlb_shootdown_finalize(i) ( (i) =(i));75 #define tlb_shootdown_start(w, x, y, z) interrupts_disable() 76 #define tlb_shootdown_finalize(i) (interrupts_restore(i)); 77 77 #define tlb_shootdown_ipi_recv() 78 78 #endif /* CONFIG_SMP */ -
kernel/generic/src/mm/as.c
rcc3c27ad rc6a7b3a 544 544 mem_backend_data_t *backend_data, uintptr_t *base, uintptr_t bound) 545 545 { 546 if ((*base != (uintptr_t) -1) && ((*base % PAGE_SIZE) != 0))546 if ((*base != (uintptr_t) -1) && !IS_ALIGNED(*base, PAGE_SIZE)) 547 547 return NULL; 548 548 … … 688 688 int as_area_resize(as_t *as, uintptr_t address, size_t size, unsigned int flags) 689 689 { 690 if (!IS_ALIGNED(address, PAGE_SIZE)) 691 return EINVAL; 692 690 693 mutex_lock(&as->lock); 691 694 … … 1350 1353 * Interrupts are assumed disabled. 1351 1354 * 1352 * @param page Faulting page.1353 * @param access Access mode that caused the page fault (i.e.1354 * read/write/exec).1355 * @param istate Pointer to the interrupted state.1355 * @param address Faulting address. 1356 * @param access Access mode that caused the page fault (i.e. 1357 * read/write/exec). 1358 * @param istate Pointer to the interrupted state. 1356 1359 * 1357 1360 * @return AS_PF_FAULT on page fault. … … 1361 1364 * 1362 1365 */ 1363 int as_page_fault(uintptr_t page, pf_access_t access, istate_t *istate) 1364 { 1366 int as_page_fault(uintptr_t address, pf_access_t access, istate_t *istate) 1367 { 1368 uintptr_t page = ALIGN_DOWN(address, PAGE_SIZE); 1365 1369 int rc = AS_PF_FAULT; 1366 1370 … … 1452 1456 task_kill_self(true); 1453 1457 } else { 1454 fault_if_from_uspace(istate, "Page fault: %p.", (void *) page);1455 panic_memtrap(istate, access, page, NULL);1458 fault_if_from_uspace(istate, "Page fault: %p.", (void *) address); 1459 panic_memtrap(istate, access, address, NULL); 1456 1460 } 1457 1461 … … 1679 1683 { 1680 1684 ASSERT(mutex_locked(&area->lock)); 1681 ASSERT( page == ALIGN_DOWN(page, PAGE_SIZE));1685 ASSERT(IS_ALIGNED(page, PAGE_SIZE)); 1682 1686 ASSERT(count); 1683 1687 … … 1963 1967 { 1964 1968 ASSERT(mutex_locked(&area->lock)); 1965 ASSERT( page == ALIGN_DOWN(page, PAGE_SIZE));1969 ASSERT(IS_ALIGNED(page, PAGE_SIZE)); 1966 1970 ASSERT(count); 1967 1971 -
kernel/generic/src/mm/backend_anon.c
rcc3c27ad rc6a7b3a 173 173 * 174 174 * @param area Pointer to the address space area. 175 * @param addr Faulting virtual address.175 * @param upage Faulting virtual page. 176 176 * @param access Access mode that caused the fault (i.e. read/write/exec). 177 177 * … … 179 179 * serviced). 180 180 */ 181 int anon_page_fault(as_area_t *area, uintptr_t addr, pf_access_t access) 182 { 183 uintptr_t upage = ALIGN_DOWN(addr, PAGE_SIZE); 181 int anon_page_fault(as_area_t *area, uintptr_t upage, pf_access_t access) 182 { 184 183 uintptr_t kpage; 185 184 uintptr_t frame; … … 187 186 ASSERT(page_table_locked(AS)); 188 187 ASSERT(mutex_locked(&area->lock)); 188 ASSERT(IS_ALIGNED(upage, PAGE_SIZE)); 189 189 190 190 if (!as_area_check_access(area, access)) -
kernel/generic/src/mm/backend_elf.c
rcc3c27ad rc6a7b3a 235 235 * 236 236 * @param area Pointer to the address space area. 237 * @param addr Faulting virtual address.237 * @param upage Faulting virtual page. 238 238 * @param access Access mode that caused the fault (i.e. 239 239 * read/write/exec). … … 242 242 * on success (i.e. serviced). 243 243 */ 244 int elf_page_fault(as_area_t *area, uintptr_t addr, pf_access_t access)244 int elf_page_fault(as_area_t *area, uintptr_t upage, pf_access_t access) 245 245 { 246 246 elf_header_t *elf = area->backend_data.elf; … … 250 250 uintptr_t frame; 251 251 uintptr_t kpage; 252 uintptr_t upage;253 252 uintptr_t start_anon; 254 253 size_t i; … … 257 256 ASSERT(page_table_locked(AS)); 258 257 ASSERT(mutex_locked(&area->lock)); 258 ASSERT(IS_ALIGNED(upage, PAGE_SIZE)); 259 259 260 260 if (!as_area_check_access(area, access)) 261 261 return AS_PF_FAULT; 262 262 263 if ( addr< ALIGN_DOWN(entry->p_vaddr, PAGE_SIZE))263 if (upage < ALIGN_DOWN(entry->p_vaddr, PAGE_SIZE)) 264 264 return AS_PF_FAULT; 265 265 266 if ( addr>= entry->p_vaddr + entry->p_memsz)266 if (upage >= entry->p_vaddr + entry->p_memsz) 267 267 return AS_PF_FAULT; 268 268 269 i = ( addr- ALIGN_DOWN(entry->p_vaddr, PAGE_SIZE)) >> PAGE_WIDTH;269 i = (upage - ALIGN_DOWN(entry->p_vaddr, PAGE_SIZE)) >> PAGE_WIDTH; 270 270 base = (uintptr_t) 271 271 (((void *) elf) + ALIGN_DOWN(entry->p_offset, PAGE_SIZE)); 272 273 /* Virtual address of faulting page */274 upage = ALIGN_DOWN(addr, PAGE_SIZE);275 272 276 273 /* Virtual address of the end of initialized part of segment */ -
kernel/generic/src/mm/backend_phys.c
rcc3c27ad rc6a7b3a 111 111 * 112 112 * @param area Pointer to the address space area. 113 * @param addr Faulting virtual address.113 * @param upage Faulting virtual page. 114 114 * @param access Access mode that caused the fault (i.e. read/write/exec). 115 115 * … … 117 117 * serviced). 118 118 */ 119 int phys_page_fault(as_area_t *area, uintptr_t addr, pf_access_t access)119 int phys_page_fault(as_area_t *area, uintptr_t upage, pf_access_t access) 120 120 { 121 121 uintptr_t base = area->backend_data.base; … … 123 123 ASSERT(page_table_locked(AS)); 124 124 ASSERT(mutex_locked(&area->lock)); 125 ASSERT(IS_ALIGNED(upage, PAGE_SIZE)); 125 126 126 127 if (!as_area_check_access(area, access)) 127 128 return AS_PF_FAULT; 128 129 129 ASSERT( addr- area->base < area->backend_data.frames * FRAME_SIZE);130 page_mapping_insert(AS, addr, base + (addr- area->base),130 ASSERT(upage - area->base < area->backend_data.frames * FRAME_SIZE); 131 page_mapping_insert(AS, upage, base + (upage - area->base), 131 132 as_area_get_flags(area)); 132 133 133 if (!used_space_insert(area, ALIGN_DOWN(addr, PAGE_SIZE), 1))134 if (!used_space_insert(area, upage, 1)) 134 135 panic("Cannot insert used space."); 135 136 -
kernel/generic/src/mm/page.c
rcc3c27ad rc6a7b3a 104 104 ASSERT(page_mapping_operations->mapping_insert); 105 105 106 page_mapping_operations->mapping_insert(as, page, frame, flags); 106 page_mapping_operations->mapping_insert(as, ALIGN_DOWN(page, PAGE_SIZE), 107 ALIGN_DOWN(frame, FRAME_SIZE), flags); 107 108 108 109 /* Repel prefetched accesses to the old mapping. */ … … 127 128 ASSERT(page_mapping_operations->mapping_remove); 128 129 129 page_mapping_operations->mapping_remove(as, page); 130 page_mapping_operations->mapping_remove(as, 131 ALIGN_DOWN(page, PAGE_SIZE)); 130 132 131 133 /* Repel prefetched accesses to the old mapping. */ … … 150 152 ASSERT(page_mapping_operations->mapping_find); 151 153 152 return page_mapping_operations->mapping_find(as, page, nolock); 154 return page_mapping_operations->mapping_find(as, 155 ALIGN_DOWN(page, PAGE_SIZE), nolock); 153 156 } 154 157 -
kernel/generic/src/sysinfo/sysinfo.c
rcc3c27ad rc6a7b3a 753 753 sysinfo_return_t ret; 754 754 ret.tag = SYSINFO_VAL_UNDEFINED; 755 ret.data.data = NULL; 756 ret.data.size = 0; 755 757 756 758 if (size > SYSINFO_MAX_PATH)
Note:
See TracChangeset
for help on using the changeset viewer.
