Changeset 9a5b556 in mainline for kernel/arch/sparc64/src
- Timestamp:
- 2006-09-12T13:03:55Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6eabb6e6
- Parents:
- 7bb6b06
- Location:
- kernel/arch/sparc64/src
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/src/cpu/cpu.c
r7bb6b06 r9a5b556 33 33 */ 34 34 35 #include <arch/asm.h> 35 36 #include <cpu.h> 36 37 #include <arch.h> 37 38 #include <arch/register.h> 38 #include <arch/asm.h>39 39 #include <print.h> 40 #include <arch/boot/boot.h> 40 41 41 42 void cpu_arch_init(void) 42 43 { 44 CPU->arch.clock_frequency = bootinfo.processor.clock_frequency; 43 45 } 44 46 … … 94 96 } 95 97 96 printf("cpu%d: manuf=%s, impl=%s, mask=%d\n", CPU->id, manuf, impl, CPU->arch.ver.mask); 98 printf("cpu%d: manuf=%s, impl=%s, mask=%d (%dMHz)\n", 99 CPU->id, manuf, impl, CPU->arch.ver.mask, CPU->arch.clock_frequency/1000000); 97 100 } 98 101 -
kernel/arch/sparc64/src/drivers/tick.c
r7bb6b06 r9a5b556 37 37 #include <arch/asm.h> 38 38 #include <arch/register.h> 39 #include <typedefs.h> 40 #include <arch/cpu.h> 41 #include <arch/boot/boot.h> 42 #include <time/clock.h> 43 #include <arch.h> 39 44 #include <debug.h> 40 #include <time/clock.h> 41 # include <typedefs.h>45 46 #define TICK_RESTART_TIME 50 /* Worst case estimate. */ 42 47 43 48 /** Initialize tick interrupt. */ … … 48 53 interrupt_register(14, "tick_int", tick_interrupt); 49 54 compare.int_dis = false; 50 compare.tick_cmpr = TICK_DELTA;55 compare.tick_cmpr = bootinfo.processor.clock_frequency/HZ; 51 56 tick_compare_write(compare.value); 52 57 tick_write(0); … … 61 66 { 62 67 softint_reg_t softint, clear; 68 uint64_t next, compare, start, stop; 63 69 64 70 softint.value = softint_read(); … … 84 90 * Restart counter. 85 91 */ 86 tick_write(0); 92 compare = CPU->arch.clock_frequency/HZ; 93 start = tick_read(); 94 next = start - compare; 95 while (next >= compare - TICK_RESTART_TIME) { 96 next -= compare; 97 CPU->missed_clock_ticks++; 98 } 99 stop = tick_read(); 100 tick_write(next + (stop - start)); 87 101 88 102 clock(); -
kernel/arch/sparc64/src/dummy.s
r7bb6b06 r9a5b556 29 29 .text 30 30 31 .global asm_delay_loop32 31 .global cpu_sleep 33 32 .global fpu_context_restore … … 39 38 .global dummy 40 39 41 asm_delay_loop:42 40 cpu_sleep: 43 41 fpu_context_restore: -
kernel/arch/sparc64/src/sparc64.c
r7bb6b06 r9a5b556 43 43 #include <arch/boot/boot.h> 44 44 #include <arch/arch.h> 45 #include <arch/asm.h> 45 46 #include <arch/mm/page.h> 46 47 #include <arch/stack.h> … … 90 91 } 91 92 93 /** Calibrate delay loop. 94 * 95 * On sparc64, we implement delay() by waiting for the TICK register to 96 * reach a pre-computed value, as opposed to performing some pre-computed 97 * amount of instructions of known duration. We set the delay_loop_const 98 * to 1 in order to neutralize the multiplication done by delay(). 99 */ 92 100 void calibrate_delay_loop(void) 93 101 { 102 CPU->delay_loop_const = 1; 103 } 104 105 /** Wait several microseconds. 106 * 107 * We assume that interrupts are already disabled. 108 * 109 * @param t Microseconds to wait. 110 */ 111 void asm_delay_loop(const uint32_t usec) 112 { 113 uint64_t stop = tick_read() + (uint64_t) usec * (uint64_t) CPU->arch.clock_frequency / 1000000; 114 115 while (tick_read() < stop) 116 ; 94 117 } 95 118 -
kernel/arch/sparc64/src/start.S
r7bb6b06 r9a5b556 61 61 */ 62 62 63 flushw ! flush all but the active register window 64 wrpr %g0, 0, %tl ! TL = 0, primary context register is used 65 66 ! Disable interrupts and disable 32-bit address masking. 67 rdpr %pstate, %g1 68 and %g1, ~(PSTATE_AM_BIT|PSTATE_IE_BIT), %g1 69 wrpr %g1, 0, %pstate 70 71 wrpr %g0, 0, %pil ! intialize %pil 63 flushw ! flush all but the active register window 64 65 wrpr %g0, 0, %tl ! TL = 0, primary context register is used 66 67 wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking. 68 69 wrpr %g0, 0, %pil ! intialize %pil 72 70 73 71 /*
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