Changeset 9a5b556 in mainline for kernel/arch/sparc64/src

Timestamp:

2006-09-12T13:03:55Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6eabb6e6

Parents:

7bb6b06

Message:

sparc64 work:

• find a CPU node and read its clock_frequency attribute
• implement asm_delay_loop()
• set TICK_COMPARE register according to processor frequency
• small improvements at random places

OpenFirmware work:

• two new functions for walking the device tree

Generic boot loader work:

• added basic string functions

Usual pile of indentation and formatting fixes.

Location:

kernel/arch/sparc64/src

Files:

• cpu/cpu.c (modified) (2 diffs)
• drivers/tick.c (modified) (4 diffs)
• dummy.s (modified) (2 diffs)
• sparc64.c (modified) (2 diffs)
• start.S (modified) (1 diff)

kernel/arch/sparc64/src/cpu/cpu.c

@@ -33 +33 @@
  */
 
+#include <arch/asm.h>
 #include <cpu.h>
 #include <arch.h>
 #include <arch/register.h>
-#include <arch/asm.h>
 #include <print.h>
+#include <arch/boot/boot.h>
 
 void cpu_arch_init(void)
 {
+        CPU->arch.clock_frequency = bootinfo.processor.clock_frequency;
 }
 
@@ -94 +96 @@
         }
 
-        printf("cpu%d: manuf=%s, impl=%s, mask=%d\n", CPU->id, manuf, impl, CPU->arch.ver.mask);
+        printf("cpu%d: manuf=%s, impl=%s, mask=%d (%dMHz)\n",
+                CPU->id, manuf, impl, CPU->arch.ver.mask, CPU->arch.clock_frequency/1000000);
 }
 

kernel/arch/sparc64/src/drivers/tick.c

@@ -37 +37 @@
 #include <arch/asm.h>
 #include <arch/register.h>
+#include <typedefs.h>
+#include <arch/cpu.h>
+#include <arch/boot/boot.h>
+#include <time/clock.h>
+#include <arch.h>
 #include <debug.h>
-#include <time/clock.h>
-#include <typedefs.h>
+
+#define TICK_RESTART_TIME       50      /* Worst case estimate. */
 
 /** Initialize tick interrupt. */
@@ -48 +53 @@
         interrupt_register(14, "tick_int", tick_interrupt);
         compare.int_dis = false;
-        compare.tick_cmpr = TICK_DELTA;
+        compare.tick_cmpr = bootinfo.processor.clock_frequency/HZ;
         tick_compare_write(compare.value);
         tick_write(0);
@@ -61 +66 @@
 {
         softint_reg_t softint, clear;
+        uint64_t next, compare, start, stop;
         
         softint.value = softint_read();
@@ -84 +90 @@
          * Restart counter.
          */
-        tick_write(0);
+        compare = CPU->arch.clock_frequency/HZ;
+        start = tick_read();
+        next = start - compare;
+        while (next >= compare - TICK_RESTART_TIME) {
+                next -= compare;
+                CPU->missed_clock_ticks++;
+        }
+        stop = tick_read();
+        tick_write(next + (stop - start));
         
         clock();

kernel/arch/sparc64/src/dummy.s

@@ -29 +29 @@
 .text
 
-.global asm_delay_loop
 .global cpu_sleep
 .global fpu_context_restore
@@ -39 +38 @@
 .global dummy
 
-asm_delay_loop:
 cpu_sleep:
 fpu_context_restore:

kernel/arch/sparc64/src/sparc64.c

@@ -43 +43 @@
 #include <arch/boot/boot.h>
 #include <arch/arch.h>
+#include <arch/asm.h>
 #include <arch/mm/page.h>
 #include <arch/stack.h>
@@ -90 +91 @@
 }
 
+/** Calibrate delay loop.
+ *
+ * On sparc64, we implement delay() by waiting for the TICK register to
+ * reach a pre-computed value, as opposed to performing some pre-computed
+ * amount of instructions of known duration. We set the delay_loop_const
+ * to 1 in order to neutralize the multiplication done by delay().
+ */
 void calibrate_delay_loop(void)
 {
+        CPU->delay_loop_const = 1;
+}
+
+/** Wait several microseconds.
+ *
+ * We assume that interrupts are already disabled.
+ *
+ * @param t Microseconds to wait.
+ */
+void asm_delay_loop(const uint32_t usec)
+{
+        uint64_t stop = tick_read() + (uint64_t) usec * (uint64_t) CPU->arch.clock_frequency / 1000000;
+
+        while (tick_read() < stop)
+                ;
 }
 

kernel/arch/sparc64/src/start.S

@@ -61 +61 @@
          */
 
-        flushw                          ! flush all but the active register window
-        wrpr %g0, 0, %tl                ! TL = 0, primary context register is used
-
-        ! Disable interrupts and disable 32-bit address masking.
-        rdpr %pstate, %g1
-        and %g1, ~(PSTATE_AM_BIT|PSTATE_IE_BIT), %g1
-        wrpr %g1, 0, %pstate
-
-        wrpr %g0, 0, %pil               ! intialize %pil
+        flushw                                  ! flush all but the active register window
+
+        wrpr %g0, 0, %tl                        ! TL = 0, primary context register is used
+
+        wrpr %g0, PSTATE_PRIV_BIT, %pstate      ! Disable interrupts and disable 32-bit address masking.
+
+        wrpr %g0, 0, %pil                       ! intialize %pil
 
         /*