Changeset 6eabb6e6 in mainline for kernel/arch/sparc64/src

Timestamp:

2006-09-13T13:16:30Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

34d9469e

Parents:

9a5b556

Message:

Support for sparc64 FPU context.

Location:

kernel/arch/sparc64/src

Files:

• asm.S (modified) (1 diff)
• dummy.s (modified) (2 diffs)
• fpu_context.c (added)
• trap/exception.c (modified) (2 diffs)
• trap/trap_table.S (modified) (6 diffs)

kernel/arch/sparc64/src/asm.S

@@ -228 +228 @@
 
 .macro WRITE_ALTERNATE_REGISTER reg, bit
+        rdpr %pstate, %g1                               ! save PSTATE.PEF
         wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
         mov %o0, \reg
+        wrpr %g0, PSTATE_PRIV_BIT, %pstate
         retl
-        wrpr %g0, PSTATE_PRIV_BIT, %pstate
+        wrpr %g1, 0, %pstate                            ! restore PSTATE.PEF
 .endm
 
 .macro READ_ALTERNATE_REGISTER reg, bit
+        rdpr %pstate, %g1                               ! save PSTATE.PEF
         wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
         mov \reg, %o0
+        wrpr %g0, PSTATE_PRIV_BIT, %pstate
         retl
-        wrpr %g0, PSTATE_PRIV_BIT, %pstate
+        wrpr %g1, 0, %pstate                            ! restore PSTATE.PEF
 .endm
 

kernel/arch/sparc64/src/dummy.s

@@ -30 +30 @@
 
 .global cpu_sleep
-.global fpu_context_restore
-.global fpu_context_save
-.global fpu_enable
-.global fpu_init
 .global sys_tls_set
 
@@ -39 +35 @@
 
 cpu_sleep:
-fpu_context_restore:
-fpu_context_save:
-fpu_enable:
-fpu_init:
 sys_tls_set:
 

kernel/arch/sparc64/src/trap/exception.c

@@ -38 +38 @@
 #include <interrupt.h>
 #include <arch/asm.h>
+#include <arch/register.h>
 #include <debug.h>
 #include <typedefs.h>
@@ -82 +83 @@
 }
 
+/** Handle fp_disabled. (0x20) */
+void fp_disabled(int n, istate_t *istate)
+{
+        fprs_reg_t fprs;
+        
+        fprs.value = fprs_read();
+        if (!fprs.fef) {
+                fprs.fef = true;
+                fprs_write(fprs.value);
+                return;
+        }
+
+#ifdef CONFIG_FPU_LAZY
+        scheduler_fpu_lazy_request();
+#else
+        fault_if_from_uspace(istate, "%s\n", __FUNCTION__);
+        dump_istate(istate);
+        panic("%s\n", __FUNCTION__);
+#endif
+}
+
 /** Handle division_by_zero. (0x28) */
 void division_by_zero(int n, istate_t *istate)

kernel/arch/sparc64/src/trap/trap_table.S

@@ -83 +83 @@
         PREEMPTIBLE_HANDLER privileged_opcode
 
+/* TT = 0x20, TL = 0, fb_disabled handler */
+.org trap_table + TT_FP_DISABLED*ENTRY_SIZE
+.global fb_disabled_tl0
+fp_disabled_tl0:
+        PREEMPTIBLE_HANDLER fp_disabled
+
 /* TT = 0x24, TL = 0, clean_window handler */
 .org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
-.global clean_window_handler_tl0
-clean_window_handler_tl0:
+.global clean_window_tl0
+clean_window_tl0:
         CLEAN_WINDOW_HANDLER
 
@@ -490 +496 @@
 /* TT = 0x24, TL > 0, clean_window handler */
 .org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
-.global clean_window_handler_tl1
-clean_window_handler_tl1:
+.global clean_window_tl1
+clean_window_tl1:
         CLEAN_WINDOW_HANDLER
 
@@ -689 +695 @@
         
         wrpr %g0, 0, %tl
-        wrpr %g0, PSTATE_PRIV_BIT, %pstate
+        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
         SAVE_GLOBALS
         
@@ -706 +712 @@
 
         RESTORE_GLOBALS
+        rdpr %pstate, %l1                       ! we must preserve the PEF bit
         wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
         wrpr %g0, 1, %tl
@@ -717 +724 @@
 
         /*
+         * Copy PSTATE.PEF to the in-register copy of TSTATE.
+         */
+        and %l1, PSTATE_PEF_BIT, %l1
+        sllx %l1, TSTATE_PSTATE_SHIFT, %l1
+        sethi %hi(TSTATE_PEF_BIT), %g4
+        andn %g1, %g4, %g1
+        or %g1, %l1, %g1
+
+        /*
          * Restore TSTATE, TPC and TNPC from saved copies.
          */
@@ -722 +738 @@
         wrpr %g2, 0, %tpc
         wrpr %g3, 0, %tnpc
+
 
         /*