Changeset 8fb1bf82 in mainline for kernel


Ignore:
Timestamp:
2010-11-25T13:42:50Z (15 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
8df8415
Parents:
a93d79a (diff), eb667613 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel
Files:
8 added
75 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/include/interrupt.h

    ra93d79a r8fb1bf82  
    3737
    3838#include <typedefs.h>
    39 #include <verify.h>
    40 #include <trace.h>
     39#include <arch/istate.h>
    4140
    4241#define IVT_ITEMS  0
    … …  
    4544#define VECTOR_TLB_SHOOTDOWN_IPI  0
    4645
    47 /*
    48  * On real hardware this stores the registers which
    49  * need to be preserved during interupts.
    50  */
    51 typedef struct istate {
    52         uintptr_t ip;
    53         uintptr_t fp;
    54         uint32_t stack[];
    55 } istate_t;
    56 
    57 NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    58     REQUIRES_EXTENT_MUTABLE(istate)
    59 {
    60         /* On real hardware this checks whether the interrupted
    61            context originated from user space. */
    62        
    63         return !(istate->ip & 0x80000000);
    64 }
    65 
    66 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
    67     uintptr_t retaddr)
    68     WRITES(&istate->ip)
    69 {
    70         /* On real hardware this sets the instruction pointer. */
    71        
    72         istate->ip = retaddr;
    73 }
    74 
    75 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    76     REQUIRES_EXTENT_MUTABLE(istate)
    77 {
    78         /* On real hardware this returns the instruction pointer. */
    79        
    80         return istate->ip;
    81 }
    82 
    83 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    84     REQUIRES_EXTENT_MUTABLE(istate)
    85 {
    86         /* On real hardware this returns the frame pointer. */
    87        
    88         return istate->fp;
    89 }
    90 
    9146#endif
    9247

  • kernel/arch/abs32le/include/mm/as.h

    ra93d79a r8fb1bf82  
    3838#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    3939
    40 #define KERNEL_ADDRESS_SPACE_START_ARCH  ((unsigned long) 0x80000000)
    41 #define KERNEL_ADDRESS_SPACE_END_ARCH    ((unsigned long) 0xffffffff)
    42 #define USER_ADDRESS_SPACE_START_ARCH    ((unsigned long) 0x00000000)
    43 #define USER_ADDRESS_SPACE_END_ARCH      ((unsigned long) 0x7fffffff)
     40#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT32_C(0x80000000)
     41#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT32_C(0xffffffff)
     42#define USER_ADDRESS_SPACE_START_ARCH    UINT32_C(0x00000000)
     43#define USER_ADDRESS_SPACE_END_ARCH      UINT32_C(0x7fffffff)
    4444
    4545#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))

  • kernel/arch/abs32le/include/mm/page.h

    ra93d79a r8fb1bf82  
    4444#ifdef KERNEL
    4545
    46 #define KA2PA(x)  (((uintptr_t) (x)) - 0x80000000)
    47 #define PA2KA(x)  (((uintptr_t) (x)) + 0x80000000)
     46#define KA2PA(x)  (((uintptr_t) (x)) - UINT32_C(0x80000000))
     47#define PA2KA(x)  (((uintptr_t) (x)) + UINT32_C(0x80000000))
    4848
    4949/*
    … …  
    6565
    6666/* Macros calculating indices for each level. */
    67 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
     67#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ffU)
    6868#define PTL1_INDEX_ARCH(vaddr)  0
    6969#define PTL2_INDEX_ARCH(vaddr)  0
    70 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
     70#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ffU)
    7171
    7272/* Get PTE address accessors for each level. */

  • kernel/arch/abs32le/include/types.h

    ra93d79a r8fb1bf82  
    5353} fncptr_t;
    5454
    55 #define PRIp  "x"  /**< Format for uintptr_t. */
    56 #define PRIs  "u"  /**< Format for size_t. */
    57 
    58 #define PRId8   "d"    /**< Format for int8_t. */
    59 #define PRId16  "d"    /**< Format for int16_t. */
    60 #define PRId32  "d"    /**< Format for int32_t. */
    61 #define PRId64  "lld"  /**< Format for int64_t. */
    62 #define PRIdn   "d"    /**< Format for native_t. */
    63 
    64 #define PRIu8   "u"    /**< Format for uint8_t. */
    65 #define PRIu16  "u"    /**< Format for uint16_t. */
    66 #define PRIu32  "u"    /**< Format for uint32_t. */
    67 #define PRIu64  "llu"  /**< Format for uint64_t. */
    68 #define PRIun   "u"    /**< Format for unative_t. */
    69 
    70 #define PRIx8   "x"    /**< Format for hexadecimal (u)int8_t. */
    71 #define PRIx16  "x"    /**< Format for hexadecimal (u)int16_t. */
    72 #define PRIx32  "x"    /**< Format for hexadecimal (u)uint32_t. */
    73 #define PRIx64  "llx"  /**< Format for hexadecimal (u)int64_t. */
    74 #define PRIxn   "x"    /**< Format for hexadecimal (u)native_t. */
     55#define PRIp   PRIx32  /**< Format for uintptr_t. */
     56#define PRIs   PRIu32  /**< Format for size_t. */
     57#define PRIdn  PRId32  /**< Format for native_t. */
     58#define PRIun  PRIu32  /**< Format for unative_t. */
     59#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
    7560
    7661#endif

  • kernel/arch/amd64/include/context.h

    ra93d79a r8fb1bf82  
    2727 */
    2828
    29 /** @addtogroup amd64   
     29/** @addtogroup amd64
    3030 * @{
    3131 */
    … …  
    4444 * panic sooner or later
    4545 */
    46 #define SP_DELTA     16
     46#define SP_DELTA  16
    4747
    4848#define context_set(c, _pc, stack, size) \

  • kernel/arch/amd64/include/context_offset.h

    ra93d79a r8fb1bf82  
    3030#define KERN_amd64_CONTEXT_OFFSET_H_
    3131
    32 #define OFFSET_SP  0x0
    33 #define OFFSET_PC  0x8
    34 #define OFFSET_RBX 0x10
    35 #define OFFSET_RBP 0x18
    36 #define OFFSET_R12 0x20
    37 #define OFFSET_R13 0x28
    38 #define OFFSET_R14 0x30
    39 #define OFFSET_R15 0x38
     32#define OFFSET_SP   0x00
     33#define OFFSET_PC   0x08
     34#define OFFSET_RBX  0x10
     35#define OFFSET_RBP  0x18
     36#define OFFSET_R12  0x20
     37#define OFFSET_R13  0x28
     38#define OFFSET_R14  0x30
     39#define OFFSET_R15  0x38
    4040
    4141#ifdef KERNEL
    42 # define OFFSET_IPL 0x40
     42        #define OFFSET_IPL 0x40
    4343#else
    44 # define OFFSET_TLS 0x40
     44        #define OFFSET_TLS 0x40
    4545#endif
    4646
    4747#ifdef __ASM__
    4848
    49 # ctx: address of the structure with saved context 
     49# ctx: address of the structure with saved context
    5050# pc: return address
    5151.macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req
    … …  
    6161.endm
    6262
    63 # ctx: address of the structure with saved context 
     63# ctx: address of the structure with saved context
    6464.macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req
    6565        movq OFFSET_R15(\ctx), %r15
    … …  
    6868        movq OFFSET_R12(\ctx), %r12
    6969        movq OFFSET_RBP(\ctx), %rbp
    70         movq OFFSET_RBX(\ctx), %rbx     
     70        movq OFFSET_RBX(\ctx), %rbx
    7171       
    7272        movq OFFSET_SP(\ctx), %rsp   # ctx->sp -> %rsp

  • kernel/arch/amd64/include/cpu.h

    ra93d79a r8fb1bf82  
    3636#define KERN_amd64_CPU_H_
    3737
    38 #define RFLAGS_CF       (1 << 0)
    39 #define RFLAGS_PF       (1 << 2)
    40 #define RFLAGS_AF       (1 << 4)
    41 #define RFLAGS_ZF       (1 << 6)
    42 #define RFLAGS_SF       (1 << 7)
    43 #define RFLAGS_TF       (1 << 8)
    44 #define RFLAGS_IF       (1 << 9)
    45 #define RFLAGS_DF       (1 << 10)
    46 #define RFLAGS_OF       (1 << 11)
    47 #define RFLAGS_NT       (1 << 14)
    48 #define RFLAGS_RF       (1 << 16)
     38#define RFLAGS_CF  (1 << 0)
     39#define RFLAGS_PF  (1 << 2)
     40#define RFLAGS_AF  (1 << 4)
     41#define RFLAGS_ZF  (1 << 6)
     42#define RFLAGS_SF  (1 << 7)
     43#define RFLAGS_TF  (1 << 8)
     44#define RFLAGS_IF  (1 << 9)
     45#define RFLAGS_DF  (1 << 10)
     46#define RFLAGS_OF  (1 << 11)
     47#define RFLAGS_NT  (1 << 14)
     48#define RFLAGS_RF  (1 << 16)
    4949
    5050#define EFER_MSR_NUM    0xc0000080

  • kernel/arch/amd64/include/debugger.h

    ra93d79a r8fb1bf82  
    4141
    4242/* Flags that are passed to breakpoint_add function */
    43 #define BKPOINT_INSTR       0x1
    44 #define BKPOINT_WRITE       0x2
    45 #define BKPOINT_READ_WRITE  0x4
     43#define BKPOINT_INSTR       0x1U
     44#define BKPOINT_WRITE       0x2U
     45#define BKPOINT_READ_WRITE  0x4U
    4646
    47 #define BKPOINT_CHECK_ZERO  0x8
     47#define BKPOINT_CHECK_ZERO  0x8U
    4848
    4949

  • kernel/arch/amd64/include/interrupt.h

    ra93d79a r8fb1bf82  
    3737
    3838#include <typedefs.h>
     39#include <arch/istate.h>
    3940#include <arch/pm.h>
    40 #include <trace.h>
    4141
    4242#define IVT_ITEMS  IDT_ITEMS
    … …  
    7171#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
    7272
    73 /** This is passed to interrupt handlers */
    74 typedef struct istate {
    75         uint64_t rax;
    76         uint64_t rbx;
    77         uint64_t rcx;
    78         uint64_t rdx;
    79         uint64_t rsi;
    80         uint64_t rdi;
    81         uint64_t rbp;
    82         uint64_t r8;
    83         uint64_t r9;
    84         uint64_t r10;
    85         uint64_t r11;
    86         uint64_t r12;
    87         uint64_t r13;
    88         uint64_t r14;
    89         uint64_t r15;
    90         uint64_t alignment;     /* align rbp_frame on multiple of 16 */
    91         uint64_t rbp_frame;     /* imitation of frame pointer linkage */
    92         uint64_t rip_frame;     /* imitation of return address linkage */
    93         uint64_t error_word;    /* real or fake error word */
    94         uint64_t rip;
    95         uint64_t cs;
    96         uint64_t rflags;
    97         uint64_t rsp;           /* only if istate_t is from uspace */
    98         uint64_t ss;            /* only if istate_t is from uspace */
    99 } istate_t;
    100 
    101 /** Return true if exception happened while in userspace */
    102 NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    103 {
    104         return !(istate->rip & 0x8000000000000000);
    105 }
    106 
    107 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
    108     uintptr_t retaddr)
    109 {
    110         istate->rip = retaddr;
    111 }
    112 
    113 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    114 {
    115         return istate->rip;
    116 }
    117 
    118 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    119 {
    120         return istate->rbp;
    121 }
    122 
    12373extern void (* disable_irqs_function)(uint16_t);
    12474extern void (* enable_irqs_function)(uint16_t);

  • kernel/arch/amd64/include/mm/as.h

    ra93d79a r8fb1bf82  
    3636#define KERN_amd64_AS_H_
    3737
     38#define ADDRESS_SPACE_HOLE_START  UINT64_C(0x0000800000000000)
     39#define ADDRESS_SPACE_HOLE_END    UINT64_C(0xffff7fffffffffff)
     40
    3841#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    3942
    40 #define KERNEL_ADDRESS_SPACE_START_ARCH  (unsigned long) 0xffff800000000000
    41 #define KERNEL_ADDRESS_SPACE_END_ARCH    (unsigned long) 0xffffffffffffffff
     43#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT64_C(0xffff800000000000)
     44#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT64_C(0xffffffffffffffff)
    4245
    43 #define USER_ADDRESS_SPACE_START_ARCH    (unsigned long) 0x0000000000000000
    44 #define USER_ADDRESS_SPACE_END_ARCH      (unsigned long) 0x00007fffffffffff
     46#define USER_ADDRESS_SPACE_START_ARCH  UINT64_C(0x0000000000000000)
     47#define USER_ADDRESS_SPACE_END_ARCH    UINT64_C(0x00007fffffffffff)
    4548
    4649#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))

  • kernel/arch/amd64/include/mm/page.h

    ra93d79a r8fb1bf82  
    5555#ifndef __ASM__
    5656
    57 #define KA2PA(x)  (((uintptr_t) (x)) - 0xffff800000000000)
    58 #define PA2KA(x)  (((uintptr_t) (x)) + 0xffff800000000000)
     57#define KA2PA(x)  (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
     58#define PA2KA(x)  (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
    5959
    6060#else /* __ASM__ */
    … …  
    7878
    7979/* Macros calculating indices into page tables in each level. */
    80 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ff)
    81 #define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ff)
    82 #define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ff)
    83 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ff)
     80#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ffU)
     81#define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ffU)
     82#define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ffU)
     83#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ffU)
    8484
    8585/* Get PTE address accessors for each level. */
    … …  
    205205        pte_t *p = &pt[i];
    206206       
    207         p->addr_12_31 = (a >> 12) & 0xfffff;
     207        p->addr_12_31 = (a >> 12) & UINT32_C(0xfffff);
    208208        p->addr_32_51 = a >> 32;
    209209}

  • kernel/arch/amd64/include/pm.h

    ra93d79a r8fb1bf82  
    7575#define AR_WRITABLE   (1 << 1)
    7676#define AR_READABLE   (1 << 1)
    77 #define AR_TSS        (0x09)
    78 #define AR_INTERRUPT  (0x0e)
    79 #define AR_TRAP       (0x0f)
     77#define AR_TSS        (0x09U)
     78#define AR_INTERRUPT  (0x0eU)
     79#define AR_TRAP       (0x0fU)
    8080
    8181#define DPL_KERNEL  (PL_KERNEL << 5)
    … …  
    8383
    8484#define TSS_BASIC_SIZE  104
    85 #define TSS_IOMAP_SIZE  (16 * 1024 + 1)  /* 16K for bitmap + 1 terminating byte for convenience */
     85#define TSS_IOMAP_SIZE  (8 * 1024 + 1)  /* 8K for bitmap + 1 terminating byte for convenience */
    8686
    8787#define IO_PORTS  (64 * 1024)

  • kernel/arch/amd64/include/types.h

    ra93d79a r8fb1bf82  
    5050} fncptr_t;
    5151
    52 /* Formats for uintptr_t, size_t */
    53 #define PRIp  "llx"
    54 #define PRIs  "llu"
    55 
    56 /* Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
    57 #define PRId8   "d"
    58 #define PRId16  "d"
    59 #define PRId32  "d"
    60 #define PRId64  "lld"
    61 #define PRIdn   "lld"
    62 
    63 #define PRIu8   "u"
    64 #define PRIu16  "u"
    65 #define PRIu32  "u"
    66 #define PRIu64  "llu"
    67 #define PRIun   "llu"
    68 
    69 #define PRIx8   "x"
    70 #define PRIx16  "x"
    71 #define PRIx32  "x"
    72 #define PRIx64  "llx"
    73 #define PRIxn   "llx"
     52#define PRIp   PRIx64  /**< Format for uintptr_t. */
     53#define PRIs   PRIu64  /**< Format for size_t. */
     54#define PRIdn  PRId64  /**< Format for native_t. */
     55#define PRIun  PRIu64  /**< Format for unative_t. */
     56#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
    7457
    7558#endif

  • kernel/arch/amd64/src/asm.S

    ra93d79a r8fb1bf82  
    9595memcpy_from_uspace_failover_address:
    9696memcpy_to_uspace_failover_address:
    97         xorq %rax, %rax         /* return 0, failure */
     97        xorl %eax, %eax         /* return 0, failure */
    9898        ret
    9999
    … …  
    143143
    144144set_efer_flag:
    145         movq $0xc0000080, %rcx
     145        movl $0xc0000080, %ecx
    146146        rdmsr
    147147        btsl %edi, %eax
    … …  
    150150
    151151read_efer_flag:
    152         movq $0xc0000080, %rcx
     152        movl $0xc0000080, %ecx
    153153        rdmsr
    154154        ret
    … …  
    243243         * Stop stack traces here if we came from userspace.
    244244         */
    245         xorq %rdx, %rdx
     245        xorl %edx, %edx
    246246        cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp)
    247247        cmovnzq %rdx, %rbp
    … …  
    386386        movq ISTATE_OFFSET_RSP(%rsp), %rsp
    387387
     388        /*
     389         * Clear the rest of the scratch registers to prevent information leak.
     390         * The 32-bit XOR on the low GPRs actually clears the entire 64-bit
     391         * register and the instruction is shorter.
     392         */
     393        xorl %edx, %edx
     394        xorl %esi, %esi
     395        xorl %edi, %edi
     396        xorq %r8, %r8
     397        xorq %r9, %r9
     398        xorq %r10, %r10
     399
    388400        sysretq
    389401
    … …  
    413425        movq %rdi, %rsi
    414426        movq $(PA2KA(0xb8000)), %rdi  /* base of EGA text mode memory */
    415         xorq %rax, %rax
     427        xorl %eax, %eax
    416428       
    417429        /* Read bits 8 - 15 of the cursor address */
    … …  
    493505                movq $(PA2KA(0xb80a0)), %rsi
    494506                movq $(PA2KA(0xb8000)), %rdi
    495                 movq $480, %rcx
     507                movl $480, %ecx
    496508                rep movsq
    497509               
    498510                /* Clear the 24th row */
    499                 xorq %rax, %rax
    500                 movq $20, %rcx
     511                xorl %eax, %eax
     512                movl $20, %ecx
    501513                rep stosq
    502514               

  • kernel/arch/amd64/src/boot/boot.S

    ra93d79a r8fb1bf82  
    516516                movq $(PA2KA(0xb80a0)), %rsi
    517517                movq $(PA2KA(0xb8000)), %rdi
    518                 movq $480, %rcx
     518                movl $480, %ecx
    519519                rep movsq
    520520               
    521521                /* Clear the 24th row */
    522                 xorq %rax, %rax
    523                 movq $20, %rcx
     522                xorl %eax, %eax
     523                movl $20, %ecx
    524524                rep stosq
    525525               

  • kernel/arch/amd64/src/boot/memmap.c

    ra93d79a r8fb1bf82  
    3535#include <arch/boot/memmap.h>
    3636
    37 uint8_t e820counter = 0xff;
     37uint8_t e820counter = 0xffU;
    3838e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
    3939

  • kernel/arch/amd64/src/context.S

    ra93d79a r8fb1bf82  
    4545        CONTEXT_SAVE_ARCH_CORE %rdi %rdx
    4646       
    47         xorq %rax, %rax       # context_save returns 1
    48         incq %rax
     47        xorl %eax, %eax       # context_save returns 1
     48        incl %eax
    4949        ret
    5050
    … …  
    6060        movq %rdx, (%rsp)
    6161       
    62         xorq %rax, %rax       # context_restore returns 0
     62        xorl %eax, %eax       # context_restore returns 0
    6363        ret

  • kernel/arch/amd64/src/cpu/cpu.c

    ra93d79a r8fb1bf82  
    4747 * Contains only non-MP-Specification specific SMP code.
    4848 */
    49 #define AMD_CPUID_EBX  0x68747541
    50 #define AMD_CPUID_ECX  0x444d4163
    51 #define AMD_CPUID_EDX  0x69746e65
     49#define AMD_CPUID_EBX  UINT32_C(0x68747541)
     50#define AMD_CPUID_ECX  UINT32_C(0x444d4163)
     51#define AMD_CPUID_EDX  UINT32_C(0x69746e65)
    5252
    53 #define INTEL_CPUID_EBX  0x756e6547
    54 #define INTEL_CPUID_ECX  0x6c65746e
    55 #define INTEL_CPUID_EDX  0x49656e69
    56 
     53#define INTEL_CPUID_EBX  UINT32_C(0x756e6547)
     54#define INTEL_CPUID_ECX  UINT32_C(0x6c65746e)
     55#define INTEL_CPUID_EDX  UINT32_C(0x49656e69)
    5756
    5857enum vendor {

  • kernel/arch/amd64/src/ddi/ddi.c

    ra93d79a r8fb1bf82  
    126126                bitmap_initialize(&iomap, CPU->arch.tss->iomap,
    127127                    TSS_IOMAP_SIZE * 8);
    128                 bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);
     128                bitmap_copy(&iomap, &TASK->arch.iomap, bits);
    129129               
     130                /*
     131                 * Set the trailing bits in the last byte of the map to disable
     132                 * I/O access.
     133                 */
     134                bitmap_set_range(&iomap, bits, ALIGN_UP(bits, 8) - bits);
    130135                /*
    131136                 * It is safe to set the trailing eight bits because of the
    132137                 * extra convenience byte in TSS_IOMAP_SIZE.
    133138                 */
    134                 bitmap_set_range(&iomap, ALIGN_UP(TASK->arch.iomap.bits, 8), 8);
     139                bitmap_set_range(&iomap, ALIGN_UP(bits, 8), 8);
    135140        }
    136141        irq_spinlock_unlock(&TASK->lock, false);

  • kernel/arch/amd64/src/debugger.c

    ra93d79a r8fb1bf82  
    126126        /* Disable breakpoint in DR7 */
    127127        unative_t dr7 = read_dr7();
    128         dr7 &= ~(0x2 << (curidx * 2));
     128        dr7 &= ~(0x02U << (curidx * 2));
    129129       
    130130        /* Setup DR register */
    … …  
    147147               
    148148                /* Set type to requested breakpoint & length*/
    149                 dr7 &= ~(0x3 << (16 + 4 * curidx));
    150                 dr7 &= ~(0x3 << (18 + 4 * curidx));
     149                dr7 &= ~(0x03U << (16 + 4 * curidx));
     150                dr7 &= ~(0x03U << (18 + 4 * curidx));
    151151               
    152152                if (!(flags & BKPOINT_INSTR)) {
    153153#ifdef __32_BITS__
    154                         dr7 |= ((unative_t) 0x3) << (18 + 4 * curidx);
     154                        dr7 |= ((unative_t) 0x03U) << (18 + 4 * curidx);
    155155#endif
    156156                       
    157157#ifdef __64_BITS__
    158                         dr7 |= ((unative_t) 0x2) << (18 + 4 * curidx);
     158                        dr7 |= ((unative_t) 0x02U) << (18 + 4 * curidx);
    159159#endif
    160160                       
    161161                        if ((flags & BKPOINT_WRITE))
    162                                 dr7 |= ((unative_t) 0x1) << (16 + 4 * curidx);
     162                                dr7 |= ((unative_t) 0x01U) << (16 + 4 * curidx);
    163163                        else if ((flags & BKPOINT_READ_WRITE))
    164                                 dr7 |= ((unative_t) 0x3) << (16 + 4 * curidx);
     164                                dr7 |= ((unative_t) 0x03U) << (16 + 4 * curidx);
    165165                }
    166166               
    167167                /* Enable global breakpoint */
    168                 dr7 |= 0x2 << (curidx * 2);
     168                dr7 |= 0x02U << (curidx * 2);
    169169               
    170170                write_dr7(dr7);
    … …  
    260260        }
    261261       
    262         cur->address = NULL;
     262        cur->address = (uintptr_t) NULL;
    263263       
    264264        setup_dr(slot);
    … …  
    313313        unsigned int i;
    314314        for (i = 0; i < BKPOINTS_MAX; i++)
    315                 breakpoints[i].address = NULL;
     315                breakpoints[i].address = (uintptr_t) NULL;
    316316       
    317317#ifdef CONFIG_KCONSOLE

  • kernel/arch/amd64/src/pm.c

    ra93d79a r8fb1bf82  
    2828 */
    2929
    30 /** @addtogroup amd64   
     30/** @addtogroup amd64
    3131 * @{
    3232 */
    … …  
    5252        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    5353        /* KTEXT descriptor */
    54         { .limit_0_15  = 0xffff,
    55           .base_0_15   = 0, 
    56           .base_16_23  = 0, 
    57           .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 
    58           .limit_16_19 = 0xf,
    59           .available   = 0, 
    60           .longmode    = 1, 
     54        { .limit_0_15  = 0xffffU,
     55          .base_0_15   = 0,
     56          .base_16_23  = 0,
     57          .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
     58          .limit_16_19 = 0x0fU,
     59          .available   = 0,
     60          .longmode    = 1,
    6161          .special     = 0,
    62           .granularity = 1, 
     62          .granularity = 1,
    6363          .base_24_31  = 0 },
    6464        /* KDATA descriptor */
    65         { .limit_0_15  = 0xffff,
    66           .base_0_15   = 0, 
    67           .base_16_23  = 0, 
    68           .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 
    69           .limit_16_19 = 0xf,
    70           .available   = 0, 
    71           .longmode    = 0, 
    72           .special     = 0, 
    73           .granularity = 1, 
     65        { .limit_0_15  = 0xffffU,
     66          .base_0_15   = 0,
     67          .base_16_23  = 0,
     68          .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
     69          .limit_16_19 = 0x0fU,
     70          .available   = 0,
     71          .longmode    = 0,
     72          .special     = 0,
     73          .granularity = 1,
    7474          .base_24_31  = 0 },
    7575        /* UDATA descriptor */
    76         { .limit_0_15  = 0xffff,
    77           .base_0_15   = 0, 
    78           .base_16_23  = 0, 
    79           .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 
    80           .limit_16_19 = 0xf,
    81           .available   = 0, 
    82           .longmode    = 0, 
    83           .special     = 1, 
    84           .granularity = 1, 
     76        { .limit_0_15  = 0xffffU,
     77          .base_0_15   = 0,
     78          .base_16_23  = 0,
     79          .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
     80          .limit_16_19 = 0x0fU,
     81          .available   = 0,
     82          .longmode    = 0,
     83          .special     = 1,
     84          .granularity = 1,
    8585          .base_24_31  = 0 },
    8686        /* UTEXT descriptor */
    87         { .limit_0_15  = 0xffff,
    88           .base_0_15   = 0, 
    89           .base_16_23  = 0, 
    90           .access      = AR_PRESENT | AR_CODE | DPL_USER, 
    91           .limit_16_19 = 0xf,
    92           .available   = 0, 
    93           .longmode    = 1, 
    94           .special     = 0, 
    95           .granularity = 1, 
     87        { .limit_0_15  = 0xffffU,
     88          .base_0_15   = 0,
     89          .base_16_23  = 0,
     90          .access      = AR_PRESENT | AR_CODE | DPL_USER,
     91          .limit_16_19 = 0x0fU,
     92          .available   = 0,
     93          .longmode    = 1,
     94          .special     = 0,
     95          .granularity = 1,
    9696          .base_24_31  = 0 },
    9797        /* KTEXT 32-bit protected, for protected mode before long mode */
    98         { .limit_0_15  = 0xffff,
    99           .base_0_15   = 0, 
    100           .base_16_23  = 0, 
    101           .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 
    102           .limit_16_19 = 0xf,
    103           .available   = 0, 
    104           .longmode    = 0, 
     98        { .limit_0_15  = 0xffffU,
     99          .base_0_15   = 0,
     100          .base_16_23  = 0,
     101          .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
     102          .limit_16_19 = 0x0fU,
     103          .available   = 0,
     104          .longmode    = 0,
    105105          .special     = 1,
    106           .granularity = 1, 
     106          .granularity = 1,
    107107          .base_24_31  = 0 },
    108108        /* TSS descriptor - set up will be completed later,
    … …  
    111111        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    112112        /* VESA Init descriptor */
    113 #ifdef CONFIG_FB       
    114         { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
    115           0xf, 0, 0, 0, 0, 0
     113#ifdef CONFIG_FB
     114        {
     115                0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
     116                    0xf, 0, 0, 0, 0, 0
    116117        }
    117118#endif
    … …  
    129130{
    130131        tss_descriptor_t *td = (tss_descriptor_t *) d;
    131 
    132         td->base_0_15 = base & 0xffff;
    133         td->base_16_23 = ((base) >> 16) & 0xff;
    134         td->base_24_31 = ((base) >> 24) & 0xff;
     132       
     133        td->base_0_15 = base & 0xffffU;
     134        td->base_16_23 = ((base) >> 16) & 0xffU;
     135        td->base_24_31 = ((base) >> 24) & 0xffU;
    135136        td->base_32_63 = ((base) >> 32);
    136137}
    … …  
    140141        tss_descriptor_t *td = (tss_descriptor_t *) d;
    141142       
    142         td->limit_0_15 = limit & 0xffff;
    143         td->limit_16_19 = (limit >> 16) & 0xf;
     143        td->limit_0_15 = limit & 0xffffU;
     144        td->limit_16_19 = (limit >> 16) & 0x0fU;
    144145}
    145146
    … …  
    149150         * Offset is a linear address.
    150151         */
    151         d->offset_0_15 = offset & 0xffff;
    152         d->offset_16_31 = offset >> 16 & 0xffff;
     152        d->offset_0_15 = offset & 0xffffU;
     153        d->offset_16_31 = (offset >> 16) & 0xffffU;
    153154        d->offset_32_63 = offset >> 32;
    154155}
    … …  
    165166{
    166167        idescriptor_t *d;
    167         int i;
    168 
     168        unsigned int i;
     169       
    169170        for (i = 0; i < IDT_ITEMS; i++) {
    170171                d = &idt[i];
    171 
     172               
    172173                d->unused = 0;
    173174                d->selector = GDT_SELECTOR(KTEXT_DES);
    174 
     175               
    175176                d->present = 1;
    176                 d->type = AR_INTERRUPT; /* masking interrupt */
     177                d->type = AR_INTERRUPT;  /* masking interrupt */
    177178        }
    178 
     179       
    179180        d = &idt[0];
    180181        idt_setoffset(d++, (uintptr_t) &int_0);

  • kernel/arch/arm32/include/exception.h

    ra93d79a r8fb1bf82  
    3939
    4040#include <typedefs.h>
    41 #include <arch/regutils.h>
    42 #include <trace.h>
     41#include <arch/istate.h>
    4342
    4443/** If defined, forces using of high exception vectors. */
    … …  
    8584extern uintptr_t exc_stack;
    8685
    87 /** Struct representing CPU state saved when an exception occurs. */
    88 typedef struct istate {
    89         uint32_t spsr;
    90         uint32_t sp;
    91         uint32_t lr;
    92        
    93         uint32_t r0;
    94         uint32_t r1;
    95         uint32_t r2;
    96         uint32_t r3;
    97         uint32_t r4;
    98         uint32_t r5;
    99         uint32_t r6;
    100         uint32_t r7;
    101         uint32_t r8;
    102         uint32_t r9;
    103         uint32_t r10;
    104         uint32_t fp;
    105         uint32_t r12;
    106        
    107         uint32_t pc;
    108 } istate_t;
    109 
    110 /** Set Program Counter member of given istate structure.
    111  *
    112  * @param istate  istate structure
    113  * @param retaddr new value of istate's PC member
    114  *
    115  */
    116 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
    117     uintptr_t retaddr)
    118 {
    119         istate->pc = retaddr;
    120 }
    121 
    122 /** Return true if exception happened while in userspace. */
    123 NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    124 {
    125         return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
    126 }
    127 
    128 /** Return Program Counter member of given istate structure. */
    129 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    130 {
    131         return istate->pc;
    132 }
    133 
    134 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    135 {
    136         return istate->fp;
    137 }
    138 
    13986extern void install_exception_handlers(void);
    14087extern void exception_init(void);

  • kernel/arch/arm32/include/types.h

    ra93d79a r8fb1bf82  
    5757} fncptr_t;
    5858
    59 #define PRIp "x"  /**< Format for uintptr_t. */
    60 #define PRIs "u"  /**< Format for size_t. */
    61 
    62 #define PRId8 "d"     /**< Format for int8_t. */
    63 #define PRId16 "d"    /**< Format for int16_t. */
    64 #define PRId32 "d"    /**< Format for int32_t. */
    65 #define PRId64 "lld"  /**< Format for int64_t. */
    66 #define PRIdn "d"     /**< Format for native_t. */
    67 
    68 #define PRIu8 "u"     /**< Format for uint8_t. */
    69 #define PRIu16 "u"    /**< Format for uint16_t. */
    70 #define PRIu32 "u"    /**< Format for uint32_t. */
    71 #define PRIu64 "llu"  /**< Format for uint64_t. */
    72 #define PRIun "u"     /**< Format for unative_t. */
    73 
    74 #define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
    75 #define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
    76 #define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
    77 #define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
    78 #define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
     59#define PRIp   PRIx32  /**< Format for uintptr_t. */
     60#define PRIs   PRIu32  /**< Format for size_t. */
     61#define PRIdn  PRId32  /**< Format for native_t. */
     62#define PRIun  PRIu32  /**< Format for unative_t. */
     63#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
    7964
    8065#endif

  • kernel/arch/ia32/include/boot/boot.h

    ra93d79a r8fb1bf82  
    3838#define BOOT_OFFSET      0x108000
    3939#define AP_BOOT_OFFSET   0x8000
    40 #define BOOT_STACK_SIZE  0x400
     40#define BOOT_STACK_SIZE  0x0400
    4141
    4242#define MULTIBOOT_HEADER_MAGIC  0x1BADB002

  • kernel/arch/ia32/include/boot/memmap.h

    ra93d79a r8fb1bf82  
    7070
    7171extern e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
    72 extern uint8_t e820counter; 
     72extern uint8_t e820counter;
    7373
    7474#endif

  • kernel/arch/ia32/include/context.h

    ra93d79a r8fb1bf82  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    4040#include <typedefs.h>
    4141
    42 #define STACK_ITEM_SIZE 4
     42#define STACK_ITEM_SIZE  4
    4343
    4444/*
    … …  
    4848 * One item is put onto stack to support get_stack_base().
    4949 */
    50 #define SP_DELTA        (8 + STACK_ITEM_SIZE)
     50#define SP_DELTA  (8 + STACK_ITEM_SIZE)
    5151
    5252#define context_set(c, _pc, stack, size) \

  • kernel/arch/ia32/include/context_offset.h

    ra93d79a r8fb1bf82  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_CONTEXT_OFFSET_H_
    3737
    38 #define OFFSET_SP  0x0
    39 #define OFFSET_PC  0x4
    40 #define OFFSET_EBX 0x8
    41 #define OFFSET_ESI 0xC
    42 #define OFFSET_EDI 0x10
    43 #define OFFSET_EBP 0x14
     38#define OFFSET_SP   0x00
     39#define OFFSET_PC   0x04
     40#define OFFSET_EBX  0x08
     41#define OFFSET_ESI  0x0C
     42#define OFFSET_EDI  0x10
     43#define OFFSET_EBP  0x14
    4444
    45 #ifdef KERNEL 
    46 # define OFFSET_IPL 0x18
     45#ifdef KERNEL
     46        #define OFFSET_IPL 0x18
    4747#else
    48 # define OFFSET_TLS 0x18
     48        #define OFFSET_TLS 0x18
    4949#endif
    5050
     51#ifdef __ASM__
    5152
    52 #ifdef __ASM__
    53 
    54 # ctx: address of the structure with saved context
     53# ctx: address of the structure with saved context
    5554# pc: return address
    5655
    5756.macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req
    58         movl %esp,OFFSET_SP(\ctx)       # %esp -> ctx->sp       
     57        movl %esp,OFFSET_SP(\ctx)       # %esp -> ctx->sp
    5958        movl \pc,OFFSET_PC(\ctx)        # %eip -> ctx->pc
    60         movl %ebx,OFFSET_EBX(\ctx)      # %ebx -> ctx->ebx     
    61         movl %esi,OFFSET_ESI(\ctx)      # %esi -> ctx->esi     
    62         movl %edi,OFFSET_EDI(\ctx)      # %edi -> ctx->edi     
    63         movl %ebp,OFFSET_EBP(\ctx)      # %ebp -> ctx->ebp     
     59        movl %ebx,OFFSET_EBX(\ctx)      # %ebx -> ctx->ebx
     60        movl %esi,OFFSET_ESI(\ctx)      # %esi -> ctx->esi
     61        movl %edi,OFFSET_EDI(\ctx)      # %edi -> ctx->edi
     62        movl %ebp,OFFSET_EBP(\ctx)      # %ebp -> ctx->ebp
    6463.endm
    6564
    66 # ctx: address of the structure with saved context 
     65# ctx: address of the structure with saved context
    6766
    6867.macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req
    … …  
    7574.endm
    7675
    77 #endif /* __ASM__ */ 
     76#endif /* __ASM__ */
    7877
    7978#endif
    … …  
    8180/** @}
    8281 */
    83 

  • kernel/arch/ia32/include/cpu.h

    ra93d79a r8fb1bf82  
    4444
    4545/* Support for SYSENTER and SYSEXIT */
    46 #define IA32_MSR_SYSENTER_CS    0x174
    47 #define IA32_MSR_SYSENTER_ESP   0x175
    48 #define IA32_MSR_SYSENTER_EIP   0x176
     46#define IA32_MSR_SYSENTER_CS   0x174U
     47#define IA32_MSR_SYSENTER_ESP  0x175U
     48#define IA32_MSR_SYSENTER_EIP  0x176U
    4949
    5050#ifndef __ASM__

  • kernel/arch/ia32/include/drivers/i8259.h

    ra93d79a r8fb1bf82  
    3939#include <arch/interrupt.h>
    4040
    41 #define PIC_PIC0PORT1  ((ioport8_t *) 0x20)
    42 #define PIC_PIC0PORT2  ((ioport8_t *) 0x21)
    43 #define PIC_PIC1PORT1  ((ioport8_t *) 0xa0)
    44 #define PIC_PIC1PORT2  ((ioport8_t *) 0xa1)
     41#define PIC_PIC0PORT1  ((ioport8_t *) 0x20U)
     42#define PIC_PIC0PORT2  ((ioport8_t *) 0x21U)
     43#define PIC_PIC1PORT1  ((ioport8_t *) 0xa0U)
     44#define PIC_PIC1PORT2  ((ioport8_t *) 0xa1U)
    4545
    4646#define PIC_NEEDICW4  (1 << 0)

  • kernel/arch/ia32/include/interrupt.h

    ra93d79a r8fb1bf82  
    3737
    3838#include <typedefs.h>
     39#include <arch/istate.h>
    3940#include <arch/pm.h>
    40 #include <trace.h>
    4141
    4242#define IVT_ITEMS  IDT_ITEMS
    … …  
    7171#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
    7272
    73 typedef struct istate {
    74         /*
    75          * The strange order of the GPRs is given by the requirement to use the
    76          * istate structure for both regular interrupts and exceptions as well
    77          * as for syscall handlers which use this order as an optimization.
    78          */
    79         uint32_t edx;
    80         uint32_t ecx;
    81         uint32_t ebx;
    82         uint32_t esi;
    83         uint32_t edi;
    84         uint32_t ebp;
    85         uint32_t eax;
    86        
    87         uint32_t ebp_frame;  /* imitation of frame pointer linkage */
    88         uint32_t eip_frame;  /* imitation of return address linkage */
    89        
    90         uint32_t gs;
    91         uint32_t fs;
    92         uint32_t es;
    93         uint32_t ds;
    94        
    95         uint32_t error_word;  /* real or fake error word */
    96         uint32_t eip;
    97         uint32_t cs;
    98         uint32_t eflags;
    99         uint32_t esp;         /* only if istate_t is from uspace */
    100         uint32_t ss;          /* only if istate_t is from uspace */
    101 } istate_t;
    102 
    103 /** Return true if exception happened while in userspace */
    104 NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    105 {
    106         return !(istate->eip & 0x80000000);
    107 }
    108 
    109 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
    110     uintptr_t retaddr)
    111 {
    112         istate->eip = retaddr;
    113 }
    114 
    115 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    116 {
    117         return istate->eip;
    118 }
    119 
    120 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    121 {
    122         return istate->ebp;
    123 }
    124 
    12573extern void (* disable_irqs_function)(uint16_t);
    12674extern void (* enable_irqs_function)(uint16_t);

  • kernel/arch/ia32/include/mm/as.h

    ra93d79a r8fb1bf82  
    3636#define KERN_ia32_AS_H_
    3737
    38 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      0
     38#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    3939
    40 #define KERNEL_ADDRESS_SPACE_START_ARCH         ((unsigned long) 0x80000000)
    41 #define KERNEL_ADDRESS_SPACE_END_ARCH           ((unsigned long) 0xffffffff)
    42 #define USER_ADDRESS_SPACE_START_ARCH           ((unsigned long) 0x00000000)
    43 #define USER_ADDRESS_SPACE_END_ARCH             ((unsigned long) 0x7fffffff)
     40#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT32_C(0x80000000)
     41#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT32_C(0xffffffff)
     42#define USER_ADDRESS_SPACE_START_ARCH    UINT32_C(0x00000000)
     43#define USER_ADDRESS_SPACE_END_ARCH      UINT32_C(0x7fffffff)
    4444
    45 #define USTACK_ADDRESS_ARCH     (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
     45#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
    4646
    4747typedef struct {
    … …  
    5050#include <genarch/mm/as_pt.h>
    5151
    52 #define as_constructor_arch(as, flags)          (as != as)
    53 #define as_destructor_arch(as)                  (as != as)
    54 #define as_create_arch(as, flags)               (as != as)
     52#define as_constructor_arch(as, flags)  (as != as)
     53#define as_destructor_arch(as)          (as != as)
     54#define as_create_arch(as, flags)       (as != as)
    5555#define as_install_arch(as)
    5656#define as_deinstall_arch(as)

  • kernel/arch/ia32/include/mm/page.h

    ra93d79a r8fb1bf82  
    3939#include <trace.h>
    4040
    41 #define PAGE_WIDTH      FRAME_WIDTH
    42 #define PAGE_SIZE       FRAME_SIZE
     41#define PAGE_WIDTH  FRAME_WIDTH
     42#define PAGE_SIZE   FRAME_SIZE
    4343
    4444#ifdef KERNEL
    4545
    4646#ifndef __ASM__
    47 #       define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
    48 #       define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
    49 #else
    50 #       define KA2PA(x) ((x) - 0x80000000)
    51 #       define PA2KA(x) ((x) + 0x80000000)
    52 #endif
     47
     48#define KA2PA(x)  (((uintptr_t) (x)) - UINT32_C(0x80000000))
     49#define PA2KA(x)  (((uintptr_t) (x)) + UINT32_C(0x80000000))
     50
     51#else /* __ASM__ */
     52
     53#define KA2PA(x)  ((x) - 0x80000000)
     54#define PA2KA(x)  ((x) + 0x80000000)
     55
     56#endif /* __ASM__ */
    5357
    5458/*
    … …  
    5862
    5963/* Number of entries in each level. */
    60 #define PTL0_ENTRIES_ARCH       1024
    61 #define PTL1_ENTRIES_ARCH       0
    62 #define PTL2_ENTRIES_ARCH       0
    63 #define PTL3_ENTRIES_ARCH       1024
     64#define PTL0_ENTRIES_ARCH  1024
     65#define PTL1_ENTRIES_ARCH  0
     66#define PTL2_ENTRIES_ARCH  0
     67#define PTL3_ENTRIES_ARCH  1024
    6468
    6569/* Page table sizes for each level. */
    66 #define PTL0_SIZE_ARCH          ONE_FRAME
    67 #define PTL1_SIZE_ARCH          0
    68 #define PTL2_SIZE_ARCH          0
    69 #define PTL3_SIZE_ARCH          ONE_FRAME
     70#define PTL0_SIZE_ARCH  ONE_FRAME
     71#define PTL1_SIZE_ARCH  0
     72#define PTL2_SIZE_ARCH  0
     73#define PTL3_SIZE_ARCH  ONE_FRAME
    7074
    7175/* Macros calculating indices for each level. */
    72 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
    73 #define PTL1_INDEX_ARCH(vaddr)  0
    74 #define PTL2_INDEX_ARCH(vaddr)  0
    75 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
     76#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ffU)
     77#define PTL1_INDEX_ARCH(vaddr)  0
     78#define PTL2_INDEX_ARCH(vaddr)  0
     79#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ffU)
    7680
    7781/* Get PTE address accessors for each level. */
    … …  
    122126#define PTE_WRITABLE_ARCH(p) \
    123127        ((p)->writeable != 0)
    124 #define PTE_EXECUTABLE_ARCH(p)                  1
     128#define PTE_EXECUTABLE_ARCH(p)  1
    125129
    126130#ifndef __ASM__
    … …  
    144148
    145149/** When bit on this position is 1, a reserved bit was set in page directory. */
    146 #define PFERR_CODE_RSVD         (1 << 3)       
     150#define PFERR_CODE_RSVD         (1 << 3)
    147151
    148152/** Page Table Entry. */

  • kernel/arch/ia32/include/pm.h

    ra93d79a r8fb1bf82  
    7575
    7676#define TSS_BASIC_SIZE  104
    77 #define TSS_IOMAP_SIZE  (16 * 1024 + 1)  /* 16K for bitmap + 1 terminating byte for convenience */
     77#define TSS_IOMAP_SIZE  (8 * 1024 + 1)  /* 8K for bitmap + 1 terminating byte for convenience */
    7878
    7979#define IO_PORTS  (64 * 1024)

  • kernel/arch/ia32/include/smp/ap.h

    ra93d79a r8fb1bf82  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */

  • kernel/arch/ia32/include/smp/apic.h

    ra93d79a r8fb1bf82  
    4949
    5050/** Delivery modes. */
    51 #define DELMOD_FIXED    0x0
    52 #define DELMOD_LOWPRI   0x1
    53 #define DELMOD_SMI      0x2
     51#define DELMOD_FIXED    0x0U
     52#define DELMOD_LOWPRI   0x1U
     53#define DELMOD_SMI      0x2U
    5454/* 0x3 reserved */
    55 #define DELMOD_NMI      0x4
    56 #define DELMOD_INIT     0x5
    57 #define DELMOD_STARTUP  0x6
    58 #define DELMOD_EXTINT   0x7
     55#define DELMOD_NMI      0x4U
     56#define DELMOD_INIT     0x5U
     57#define DELMOD_STARTUP  0x6U
     58#define DELMOD_EXTINT   0x7U
    5959
    6060/** Destination modes. */
    61 #define DESTMOD_PHYS   0x0
    62 #define DESTMOD_LOGIC  0x1
     61#define DESTMOD_PHYS   0x0U
     62#define DESTMOD_LOGIC  0x1U
    6363
    6464/** Trigger Modes. */
    65 #define TRIGMOD_EDGE   0x0
    66 #define TRIGMOD_LEVEL  0x1
     65#define TRIGMOD_EDGE   0x0U
     66#define TRIGMOD_LEVEL  0x1U
    6767
    6868/** Levels. */
    69 #define LEVEL_DEASSERT  0x0
    70 #define LEVEL_ASSERT    0x1
     69#define LEVEL_DEASSERT  0x0U
     70#define LEVEL_ASSERT    0x1U
    7171
    7272/** Destination Shorthands. */
    73 #define SHORTHAND_NONE      0x0
    74 #define SHORTHAND_SELF      0x1
    75 #define SHORTHAND_ALL_INCL  0x2
    76 #define SHORTHAND_ALL_EXCL  0x3
     73#define SHORTHAND_NONE      0x0U
     74#define SHORTHAND_SELF      0x1U
     75#define SHORTHAND_ALL_INCL  0x2U
     76#define SHORTHAND_ALL_EXCL  0x3U
    7777
    7878/** Interrupt Input Pin Polarities. */
    79 #define POLARITY_HIGH  0x0
    80 #define POLARITY_LOW   0x1
     79#define POLARITY_HIGH  0x0U
     80#define POLARITY_LOW   0x1U
    8181
    8282/** Divide Values. (Bit 2 is always 0) */
    83 #define DIVIDE_2    0x0
    84 #define DIVIDE_4    0x1
    85 #define DIVIDE_8    0x2
    86 #define DIVIDE_16   0x3
    87 #define DIVIDE_32   0x8
    88 #define DIVIDE_64   0x9
    89 #define DIVIDE_128  0xa
    90 #define DIVIDE_1    0xb
     83#define DIVIDE_2    0x0U
     84#define DIVIDE_4    0x1U
     85#define DIVIDE_8    0x2U
     86#define DIVIDE_16   0x3U
     87#define DIVIDE_32   0x8U
     88#define DIVIDE_64   0x9U
     89#define DIVIDE_128  0xaU
     90#define DIVIDE_1    0xbU
    9191
    9292/** Timer Modes. */
    93 #define TIMER_ONESHOT   0x0
    94 #define TIMER_PERIODIC  0x1
     93#define TIMER_ONESHOT   0x0U
     94#define TIMER_PERIODIC  0x1U
    9595
    9696/** Delivery status. */
    97 #define DELIVS_IDLE     0x0
    98 #define DELIVS_PENDING  0x1
     97#define DELIVS_IDLE     0x0U
     98#define DELIVS_PENDING  0x1U
    9999
    100100/** Destination masks. */
    101 #define DEST_ALL  0xff
     101#define DEST_ALL  0xffU
    102102
    103103/** Dest format models. */
    104 #define MODEL_FLAT     0xf
    105 #define MODEL_CLUSTER  0x0
     104#define MODEL_FLAT     0xfU
     105#define MODEL_CLUSTER  0x0U
    106106
    107107/** Interrupt Command Register. */
    108 #define ICRlo  (0x300 / sizeof(uint32_t))
    109 #define ICRhi  (0x310 / sizeof(uint32_t))
     108#define ICRlo  (0x300U / sizeof(uint32_t))
     109#define ICRhi  (0x310U / sizeof(uint32_t))
    110110
    111111typedef struct {
    … …  
    135135
    136136/* End Of Interrupt. */
    137 #define EOI  (0x0b0 / sizeof(uint32_t))
     137#define EOI  (0x0b0U / sizeof(uint32_t))
    138138
    139139/** Error Status Register. */
    140 #define ESR  (0x280 / sizeof(uint32_t))
     140#define ESR  (0x280U / sizeof(uint32_t))
    141141
    142142typedef union {
    … …  
    157157
    158158/* Task Priority Register */
    159 #define TPR  (0x080 / sizeof(uint32_t))
     159#define TPR  (0x080U / sizeof(uint32_t))
    160160
    161161typedef union {
    … …  
    168168
    169169/** Spurious-Interrupt Vector Register. */
    170 #define SVR  (0x0f0 / sizeof(uint32_t))
     170#define SVR  (0x0f0U / sizeof(uint32_t))
    171171
    172172typedef union {
    … …  
    181181
    182182/** Time Divide Configuration Register. */
    183 #define TDCR  (0x3e0 / sizeof(uint32_t))
     183#define TDCR  (0x3e0U / sizeof(uint32_t))
    184184
    185185typedef union {
    … …  
    192192
    193193/* Initial Count Register for Timer */
    194 #define ICRT  (0x380 / sizeof(uint32_t))
     194#define ICRT  (0x380U / sizeof(uint32_t))
    195195
    196196/* Current Count Register for Timer */
    197 #define CCRT  (0x390 / sizeof(uint32_t))
     197#define CCRT  (0x390U / sizeof(uint32_t))
    198198
    199199/** LVT Timer register. */
    200 #define LVT_Tm  (0x320 / sizeof(uint32_t))
     200#define LVT_Tm  (0x320U / sizeof(uint32_t))
    201201
    202202typedef union {
    … …  
    214214
    215215/** LVT LINT registers. */
    216 #define LVT_LINT0  (0x350 / sizeof(uint32_t))
    217 #define LVT_LINT1  (0x360 / sizeof(uint32_t))
     216#define LVT_LINT0  (0x350U / sizeof(uint32_t))
     217#define LVT_LINT1  (0x360U / sizeof(uint32_t))
    218218
    219219typedef union {
    … …  
    233233
    234234/** LVT Error register. */
    235 #define LVT_Err  (0x370 / sizeof(uint32_t))
     235#define LVT_Err  (0x370U / sizeof(uint32_t))
    236236
    237237typedef union {
    … …  
    248248
    249249/** Local APIC ID Register. */
    250 #define L_APIC_ID  (0x020 / sizeof(uint32_t))
     250#define L_APIC_ID  (0x020U / sizeof(uint32_t))
    251251
    252252typedef union {
    … …  
    259259
    260260/** Local APIC Version Register */
    261 #define LAVR       (0x030 / sizeof(uint32_t))
    262 #define LAVR_Mask  0xff
    263 
    264 #define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0) == 0x1)
    265 #define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0) == 0x0))
    266 #define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14)
     261#define LAVR       (0x030U / sizeof(uint32_t))
     262#define LAVR_Mask  0xffU
     263
     264#define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0U) == 0x1U)
     265#define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0U) == 0x0U))
     266#define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14U)
    267267
    268268/** Logical Destination Register. */
    269 #define  LDR  (0x0d0 / sizeof(uint32_t))
     269#define  LDR  (0x0d0U / sizeof(uint32_t))
    270270
    271271typedef union {
    … …  
    278278
    279279/** Destination Format Register. */
    280 #define DFR  (0x0e0 / sizeof(uint32_t))
     280#define DFR  (0x0e0U / sizeof(uint32_t))
    281281
    282282typedef union {
    … …  
    289289
    290290/* IO APIC */
    291 #define IOREGSEL  (0x00 / sizeof(uint32_t))
    292 #define IOWIN     (0x10 / sizeof(uint32_t))
    293 
    294 #define IOAPICID   0x00
    295 #define IOAPICVER  0x01
    296 #define IOAPICARB  0x02
    297 #define IOREDTBL   0x10
     291#define IOREGSEL  (0x00U / sizeof(uint32_t))
     292#define IOWIN     (0x10U / sizeof(uint32_t))
     293
     294#define IOAPICID   0x00U
     295#define IOAPICVER  0x01U
     296#define IOAPICARB  0x02U
     297#define IOREDTBL   0x10U
    298298
    299299/** I/O Register Select Register. */

  • kernel/arch/ia32/include/types.h

    ra93d79a r8fb1bf82  
    5050} fncptr_t;
    5151
    52 #define PRIp "x"  /**< Format for uintptr_t. */
    53 #define PRIs "u"  /**< Format for size_t. */
    54 
    55 #define PRId8 "d"     /**< Format for int8_t. */
    56 #define PRId16 "d"    /**< Format for int16_t. */
    57 #define PRId32 "d"    /**< Format for int32_t. */
    58 #define PRId64 "lld"  /**< Format for int64_t. */
    59 #define PRIdn "d"     /**< Format for native_t. */
    60 
    61 #define PRIu8 "u"     /**< Format for uint8_t. */
    62 #define PRIu16 "u"    /**< Format for uint16_t. */
    63 #define PRIu32 "u"    /**< Format for uint32_t. */
    64 #define PRIu64 "llu"  /**< Format for uint64_t. */
    65 #define PRIun "u"     /**< Format for unative_t. */
    66 
    67 #define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
    68 #define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
    69 #define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
    70 #define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
    71 #define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
     52#define PRIp   PRIx32  /**< Format for uintptr_t. */
     53#define PRIs   PRIu32  /**< Format for size_t. */
     54#define PRIdn  PRId32  /**< Format for native_t. */
     55#define PRIun  PRIu32  /**< Format for unative_t. */
     56#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
    7257
    7358#endif

  • kernel/arch/ia32/src/bios/bios.c

    ra93d79a r8fb1bf82  
    3636#include <typedefs.h>
    3737
    38 #define BIOS_EBDA_PTR  0x40e
     38#define BIOS_EBDA_PTR  0x40eU
    3939
    4040uintptr_t ebda = 0;
    … …  
    4343{
    4444        /* Copy the EBDA address out from BIOS Data Area */
    45         ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10;
     45        ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10U;
    4646}
    4747

  • kernel/arch/ia32/src/boot/memmap.c

    ra93d79a r8fb1bf82  
    3535#include <arch/boot/memmap.h>
    3636
    37 uint8_t e820counter = 0xff;
     37uint8_t e820counter = 0xffU;
    3838e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
    3939

  • kernel/arch/ia32/src/cpu/cpu.c

    ra93d79a r8fb1bf82  
    4949 * Contains only non-MP-Specification specific SMP code.
    5050 */
    51 #define AMD_CPUID_EBX  0x68747541
    52 #define AMD_CPUID_ECX  0x444d4163
    53 #define AMD_CPUID_EDX  0x69746e65
     51#define AMD_CPUID_EBX  UINT32_C(0x68747541)
     52#define AMD_CPUID_ECX  UINT32_C(0x444d4163)
     53#define AMD_CPUID_EDX  UINT32_C(0x69746e65)
    5454
    55 #define INTEL_CPUID_EBX  0x756e6547
    56 #define INTEL_CPUID_ECX  0x6c65746e
    57 #define INTEL_CPUID_EDX  0x49656e69
     55#define INTEL_CPUID_EBX  UINT32_C(0x756e6547)
     56#define INTEL_CPUID_ECX  UINT32_C(0x6c65746e)
     57#define INTEL_CPUID_EDX  UINT32_C(0x49656e69)
    5858
    5959
    … …  
    140140                if ((info.cpuid_ebx == AMD_CPUID_EBX)
    141141                    && (info.cpuid_ecx == AMD_CPUID_ECX)
    142                         && (info.cpuid_edx == AMD_CPUID_EDX))
     142                    && (info.cpuid_edx == AMD_CPUID_EDX))
    143143                        CPU->arch.vendor = VendorAMD;
    144144               
    145145                /*
    146146                 * Check for Intel processor.
    147                  */             
     147                 */
    148148                if ((info.cpuid_ebx == INTEL_CPUID_EBX)
    149149                    && (info.cpuid_ecx == INTEL_CPUID_ECX)
    150                         && (info.cpuid_edx == INTEL_CPUID_EDX))
     150                    && (info.cpuid_edx == INTEL_CPUID_EDX))
    151151                        CPU->arch.vendor = VendorIntel;
    152152               
    153153                cpuid(INTEL_CPUID_STANDARD, &info);
    154                 CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
    155                 CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
    156                 CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;                                             
     154                CPU->arch.family = (info.cpuid_eax >> 8) & 0x0fU;
     155                CPU->arch.model = (info.cpuid_eax >> 4) & 0x0fU;
     156                CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0fU;
    157157        }
    158158}

  • kernel/arch/ia32/src/ddi/ddi.c

    ra93d79a r8fb1bf82  
    127127                bitmap_initialize(&iomap, CPU->arch.tss->iomap,
    128128                    TSS_IOMAP_SIZE * 8);
    129                 bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);
     129                bitmap_copy(&iomap, &TASK->arch.iomap, bits);
    130130               
     131                /*
     132                 * Set the trailing bits in the last byte of the map to disable
     133                 * I/O access.
     134                 */
     135                bitmap_set_range(&iomap, bits, ALIGN_UP(bits, 8) - bits);
    131136                /*
    132137                 * It is safe to set the trailing eight bits because of the
    133138                 * extra convenience byte in TSS_IOMAP_SIZE.
    134139                 */
    135                 bitmap_set_range(&iomap, ALIGN_UP(TASK->arch.iomap.bits, 8), 8);
     140                bitmap_set_range(&iomap, ALIGN_UP(bits, 8), 8);
    136141        }
    137142        irq_spinlock_unlock(&TASK->lock, false);

  • kernel/arch/ia32/src/debug/stacktrace.c

    ra93d79a r8fb1bf82  
    3737#include <typedefs.h>
    3838
    39 #define FRAME_OFFSET_FP_PREV    0
    40 #define FRAME_OFFSET_RA         1
     39#define FRAME_OFFSET_FP_PREV  0
     40#define FRAME_OFFSET_RA       1
    4141
    4242bool kernel_stack_trace_context_validate(stack_trace_context_t *ctx)

  • kernel/arch/ia32/src/drivers/i8254.c

    ra93d79a r8fb1bf82  
    5454#include <ddi/device.h>
    5555
    56 #define CLK_PORT1  ((ioport8_t *) 0x40)
    57 #define CLK_PORT4  ((ioport8_t *) 0x43)
     56#define CLK_PORT1  ((ioport8_t *) 0x40U)
     57#define CLK_PORT4  ((ioport8_t *) 0x43U)
    5858
    5959#define CLK_CONST     1193180

  • kernel/arch/ia32/src/drivers/i8259.c

    ra93d79a r8fb1bf82  
    121121void pic_eoi(void)
    122122{
    123         pio_write_8((ioport8_t *)0x20, 0x20);
    124         pio_write_8((ioport8_t *)0xa0, 0x20);
     123        pio_write_8((ioport8_t *) 0x20, 0x20);
     124        pio_write_8((ioport8_t *) 0xa0, 0x20);
    125125}
    126126

  • kernel/arch/ia32/src/drivers/vesa.c

    ra93d79a r8fb1bf82  
    7070bool vesa_init(void)
    7171{
    72         if ((vesa_width == 0xffff) || (vesa_height == 0xffff))
     72        if ((vesa_width == 0xffffU) || (vesa_height == 0xffffU))
    7373                return false;
    7474       

  • kernel/arch/ia32/src/mm/frame.c

    ra93d79a r8fb1bf82  
    4444#include <align.h>
    4545#include <macros.h>
    46 
    4746#include <print.h>
    4847
    49 #define PHYSMEM_LIMIT32  0x07c000000ull
    50 #define PHYSMEM_LIMIT64  0x200000000ull
     48#define PHYSMEM_LIMIT32  UINT64_C(0x07c000000)
     49#define PHYSMEM_LIMIT64  UINT64_C(0x200000000)
    5150
    5251size_t hardcoded_unmapped_ktext_size = 0;

  • kernel/arch/ia32/src/smp/apic.c

    ra93d79a r8fb1bf82  
    7272 *
    7373 */
    74 volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
    75 volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
     74volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000);
     75volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000);
    7676
    7777uint32_t apic_id_mask = 0;
    … …  
    184184         * Other interrupts will be forwarded to the lowest priority CPU.
    185185         */
    186         io_apic_disable_irqs(0xffff);
     186        io_apic_disable_irqs(0xffffU);
    187187       
    188188        irq_initialize(&l_apic_timer_irq);

  • kernel/arch/ia32/src/smp/mps.c

    ra93d79a r8fb1bf82  
    5252 */
    5353
    54 #define FS_SIGNATURE  0x5f504d5f
    55 #define CT_SIGNATURE  0x504d4350
     54#define FS_SIGNATURE  UINT32_C(0x5f504d5f)
     55#define CT_SIGNATURE  UINT32_C(0x504d4350)
    5656
    5757static struct mps_fs *fs;

  • kernel/arch/ia64/include/interrupt.h

    ra93d79a r8fb1bf82  
    3737
    3838#include <typedefs.h>
    39 #include <arch/register.h>
    40 #include <trace.h>
     39#include <arch/istate.h>
    4140
    4241/** ia64 has 256 INRs. */
    … …  
    7473#define EOI  0  /**< The actual value doesn't matter. */
    7574
    76 typedef struct istate {
    77         uint128_t f2;
    78         uint128_t f3;
    79         uint128_t f4;
    80         uint128_t f5;
    81         uint128_t f6;
    82         uint128_t f7;
    83         uint128_t f8;
    84         uint128_t f9;
    85         uint128_t f10;
    86         uint128_t f11;
    87         uint128_t f12;
    88         uint128_t f13;
    89         uint128_t f14;
    90         uint128_t f15;
    91         uint128_t f16;
    92         uint128_t f17;
    93         uint128_t f18;
    94         uint128_t f19;
    95         uint128_t f20;
    96         uint128_t f21;
    97         uint128_t f22;
    98         uint128_t f23;
    99         uint128_t f24;
    100         uint128_t f25;
    101         uint128_t f26;
    102         uint128_t f27;
    103         uint128_t f28;
    104         uint128_t f29;
    105         uint128_t f30;
    106         uint128_t f31;
    107        
    108         uintptr_t ar_bsp;
    109         uintptr_t ar_bspstore;
    110         uintptr_t ar_bspstore_new;
    111         uint64_t ar_rnat;
    112         uint64_t ar_ifs;
    113         uint64_t ar_pfs;
    114         uint64_t ar_rsc;
    115         uintptr_t cr_ifa;
    116         cr_isr_t cr_isr;
    117         uintptr_t cr_iipa;
    118         psr_t cr_ipsr;
    119         uintptr_t cr_iip;
    120         uint64_t pr;
    121         uintptr_t sp;
    122        
    123         /*
    124          * The following variables are defined only for break_instruction
    125          * handler.
    126          */
    127         uint64_t in0;
    128         uint64_t in1;
    129         uint64_t in2;
    130         uint64_t in3;
    131         uint64_t in4;
    132         uint64_t in5;
    133         uint64_t in6;
    134 } istate_t;
    135 
    13675extern void *ivt;
    137 
    138 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
    139     uintptr_t retaddr)
    140 {
    141         istate->cr_iip = retaddr;
    142         istate->cr_ipsr.ri = 0;    /* return to instruction slot #0 */
    143 }
    144 
    145 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    146 {
    147         return istate->cr_iip;
    148 }
    149 
    150 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    151 {
    152         /* FIXME */
    153        
    154         return 0;
    155 }
    156 
    157 NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    158 {
    159         return (istate->cr_iip) < 0xe000000000000000ULL;
    160 }
    16176
    16277extern void general_exception(uint64_t, istate_t *);

  • kernel/arch/ia64/include/register.h

    ra93d79a r8fb1bf82  
    142142#ifndef __ASM__
    143143
     144#ifdef KERNEL
    144145#include <typedefs.h>
     146#else
     147#include <sys/types.h>
     148#endif
    145149
    146150/** Processor Status Register. */

  • kernel/arch/ia64/include/types.h

    ra93d79a r8fb1bf82  
    5252} __attribute__((may_alias)) fncptr_t;
    5353
    54 #define PRIp "lx"  /**< Format for uintptr_t. */
    55 #define PRIs "lu"  /**< Format for size_t. */
    56 
    57 #define PRId8 "d"    /**< Format for int8_t. */
    58 #define PRId16 "d"   /**< Format for int16_t. */
    59 #define PRId32 "d"   /**< Format for int32_t. */
    60 #define PRId64 "ld"  /**< Format for int64_t. */
    61 #define PRIdn "d"    /**< Format for native_t. */
    62 
    63 #define PRIu8 "u"    /**< Format for uint8_t. */
    64 #define PRIu16 "u"   /**< Format for uint16_t. */
    65 #define PRIu32 "u"   /**< Format for uint32_t. */
    66 #define PRIu64 "lu"  /**< Format for uint64_t. */
    67 #define PRIun "u"    /**< Format for unative_t. */
    68 
    69 #define PRIx8 "x"    /**< Format for hexadecimal (u)int8_t. */
    70 #define PRIx16 "x"   /**< Format for hexadecimal (u)int16_t. */
    71 #define PRIx32 "x"   /**< Format for hexadecimal (u)uint32_t. */
    72 #define PRIx64 "lx"  /**< Format for hexadecimal (u)int64_t. */
    73 #define PRIxn "x"    /**< Format for hexadecimal (u)native_t. */
     54#define PRIp   PRIx64  /**< Format for uintptr_t. */
     55#define PRIs   PRIu64  /**< Format for size_t. */
     56#define PRIdn  PRId64  /**< Format for native_t. */
     57#define PRIun  PRIu64  /**< Format for unative_t. */
     58#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
    7459
    7560#endif

  • kernel/arch/mips32/include/cp0.h

    ra93d79a r8fb1bf82  
    3636#define KERN_mips32_CP0_H_
    3737
     38#ifdef KERNEL
    3839#include <typedefs.h>
     40#else
     41#include <sys/types.h>
     42#endif
    3943
    4044#define cp0_status_ie_enabled_bit     (1 << 0)

  • kernel/arch/mips32/include/exception.h

    ra93d79a r8fb1bf82  
    3737
    3838#include <typedefs.h>
    39 #include <arch/cp0.h>
    40 #include <trace.h>
     39#include <arch/istate.h>
    4140
    4241#define EXC_Int    0
    … …  
    5958#define EXC_VCED   31
    6059
    61 typedef struct istate {
    62         /*
    63          * The first seven registers are arranged so that the istate structure
    64          * can be used both for exception handlers and for the syscall handler.
    65          */
    66         uint32_t a0;    /* arg1 */
    67         uint32_t a1;    /* arg2 */
    68         uint32_t a2;    /* arg3 */
    69         uint32_t a3;    /* arg4 */
    70         uint32_t t0;    /* arg5 */
    71         uint32_t t1;    /* arg6 */
    72         uint32_t v0;    /* arg7 */
    73         uint32_t v1;
    74         uint32_t at;
    75         uint32_t t2;
    76         uint32_t t3;
    77         uint32_t t4;
    78         uint32_t t5;
    79         uint32_t t6;
    80         uint32_t t7;
    81         uint32_t s0;
    82         uint32_t s1;
    83         uint32_t s2;
    84         uint32_t s3;
    85         uint32_t s4;
    86         uint32_t s5;
    87         uint32_t s6;
    88         uint32_t s7;
    89         uint32_t t8;
    90         uint32_t t9;
    91         uint32_t kt0;
    92         uint32_t kt1;   /* We use it as thread-local pointer */
    93         uint32_t gp;
    94         uint32_t sp;
    95         uint32_t s8;
    96         uint32_t ra;
    97        
    98         uint32_t lo;
    99         uint32_t hi;
    100        
    101         uint32_t status;        /* cp0_status */
    102         uint32_t epc;           /* cp0_epc */
    103 
    104         uint32_t alignment;     /* to make sizeof(istate_t) a multiple of 8 */
    105 } istate_t;
    106 
    107 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
    108     uintptr_t retaddr)
    109 {
    110         istate->epc = retaddr;
    111 }
    112 
    113 /** Return true if exception happened while in userspace */
    114 NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    115 {
    116         return istate->status & cp0_status_um_bit;
    117 }
    118 
    119 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    120 {
    121         return istate->epc;
    122 }
    123 
    124 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    125 {
    126         return istate->sp;
    127 }
    128 
    12960extern void exception(istate_t *istate);
    13061extern void tlb_refill_entry(void);

  • kernel/arch/mips32/include/types.h

    ra93d79a r8fb1bf82  
    5050} fncptr_t;
    5151
    52 #define PRIp "x"  /**< Format for uintptr_t. */
    53 #define PRIs "u"  /**< Format for size_t. */
    54 
    55 #define PRId8 "d"     /**< Format for int8_t. */
    56 #define PRId16 "d"    /**< Format for int16_t. */
    57 #define PRId32 "ld"   /**< Format for int32_t. */
    58 #define PRId64 "lld"  /**< Format for int64_t. */
    59 #define PRIdn "d"     /**< Format for native_t. */
    60 
    61 #define PRIu8 "u"     /**< Format for uint8_t. */
    62 #define PRIu16 "u"    /**< Format for uint16_t. */
    63 #define PRIu32 "u"    /**< Format for uint32_t. */
    64 #define PRIu64 "llu"  /**< Format for uint64_t. */
    65 #define PRIun "u"     /**< Format for unative_t. */
    66 
    67 #define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
    68 #define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
    69 #define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
    70 #define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
    71 #define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
     52#define PRIp   PRIx32  /**< Format for uintptr_t. */
     53#define PRIs   PRIu32  /**< Format for size_t. */
     54#define PRIdn  PRId32  /**< Format for native_t. */
     55#define PRIun  PRIu32  /**< Format for unative_t. */
     56#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
    7257
    7358#endif

  • kernel/arch/mips32/src/debugger.c

    ra93d79a r8fb1bf82  
    247247        smc_coherence(((uint32_t *) cur->address)[1]);
    248248       
    249         cur->address = NULL;
     249        cur->address = (uintptr_t) NULL;
    250250       
    251251        irq_spinlock_unlock(&bkpoint_lock, true);
    … …  
    289289       
    290290        for (i = 0; i < BKPOINTS_MAX; i++)
    291                 breakpoints[i].address = NULL;
     291                breakpoints[i].address = (uintptr_t) NULL;
    292292       
    293293#ifdef CONFIG_KCONSOLE
    … …  
    417417                /* Remove one-shot breakpoint */
    418418                if ((cur->flags & BKPOINT_ONESHOT))
    419                         cur->address = NULL;
     419                        cur->address = (uintptr_t) NULL;
    420420               
    421421                /* Remove in-progress flag */

  • kernel/arch/ppc32/include/types.h

    ra93d79a r8fb1bf82  
    5050} fncptr_t;
    5151
    52 /** Formats for uintptr_t, size_t */
    53 #define PRIp  "x"
    54 #define PRIs  "u"
    55 
    56 /** Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
    57 #define PRId8   "d"
    58 #define PRId16  "d"
    59 #define PRId32  "d"
    60 #define PRId64  "lld"
    61 #define PRIdn   "d"
    62 
    63 #define PRIu8   "u"
    64 #define PRIu16  "u"
    65 #define PRIu32  "u"
    66 #define PRIu64  "llu"
    67 #define PRIun   "u"
    68 
    69 #define PRIx8   "x"
    70 #define PRIx16  "x"
    71 #define PRIx32  "x"
    72 #define PRIx64  "llx"
    73 #define PRIxn   "x"
     52#define PRIp   PRIx32  /**< Format for uintptr_t. */
     53#define PRIs   PRIu32  /**< Format for size_t. */
     54#define PRIdn  PRId32  /**< Format for native_t. */
     55#define PRIun  PRIu32  /**< Format for unative_t. */
     56#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
    7457
    7558#endif

  • kernel/arch/sparc64/include/interrupt.h

    ra93d79a r8fb1bf82  
    3838
    3939#include <typedefs.h>
    40 #include <arch/regdef.h>
    41 #include <trace.h>
     40#include <arch/istate.h>
    4241
    4342#define IVT_ITEMS  15
    … …  
    5150};
    5251
    53 typedef struct istate {
    54         uint64_t tnpc;
    55         uint64_t tpc;
    56         uint64_t tstate;
    57 } istate_t;
    58 
    59 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
    60     uintptr_t retaddr)
    61 {
    62         istate->tpc = retaddr;
    63 }
    64 
    65 NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    66 {
    67         return !(istate->tstate & TSTATE_PRIV_BIT);
    68 }
    69 
    70 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    71 {
    72         return istate->tpc;
    73 }
    74 
    75 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    76 {
    77         /* TODO */
    78        
    79         return 0;
    80 }
    81 
    8252#endif
    8353

  • kernel/arch/sparc64/include/types.h

    ra93d79a r8fb1bf82  
    5252typedef uint8_t asi_t;
    5353
    54 /** Formats for uintptr_t, size_t */
    55 #define PRIp  "llx"
    56 #define PRIs  "llu"
    57 
    58 /** Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
    59 #define PRId8   "d"
    60 #define PRId16  "d"
    61 #define PRId32  "d"
    62 #define PRId64  "lld"
    63 #define PRIdn   "lld"
    64 
    65 #define PRIu8   "u"
    66 #define PRIu16  "u"
    67 #define PRIu32  "u"
    68 #define PRIu64  "llu"
    69 #define PRIun   "llu"
    70 
    71 #define PRIx8   "x"
    72 #define PRIx16  "x"
    73 #define PRIx32  "x"
    74 #define PRIx64  "llx"
    75 #define PRIxn   "llx"
     54#define PRIp   PRIx64  /**< Format for uintptr_t. */
     55#define PRIs   PRIu64  /**< Format for size_t. */
     56#define PRIdn  PRId64  /**< Format for native_t. */
     57#define PRIun  PRIu64  /**< Format for unative_t. */
     58#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
    7659
    7760#endif

  • kernel/arch/sparc64/src/mm/sun4u/frame.c

    ra93d79a r8fb1bf82  
    4141#include <macros.h>
    4242
    43 uintptr_t last_frame = NULL;
     43uintptr_t last_frame = (uintptr_t) NULL;
    4444
    4545/** Create memory zones according to information stored in memmap.

  • kernel/generic/include/ddi/ddi.h

    ra93d79a r8fb1bf82  
    5454extern unative_t sys_physmem_map(unative_t, unative_t, unative_t, unative_t);
    5555extern unative_t sys_iospace_enable(ddi_ioarg_t *);
     56extern unative_t sys_interrupt_enable(int irq, int enable);
    5657
    5758/*
    … …  
    6061extern int ddi_iospace_enable_arch(task_t *, uintptr_t, size_t);
    6162
     63
    6264#endif
    6365

  • kernel/generic/include/syscall/syscall.h

    ra93d79a r8fb1bf82  
    8080        SYS_PHYSMEM_MAP,
    8181        SYS_IOSPACE_ENABLE,
     82        SYS_INTERRUPT_ENABLE,
    8283       
    8384        SYS_SYSINFO_GET_TAG,

  • kernel/generic/include/typedefs.h

    ra93d79a r8fb1bf82  
    4040#include <arch/types.h>
    4141
    42 #define NULL  0
     42#define NULL    ((void *) 0)
    4343
    4444#define false  0

  • kernel/generic/src/adt/bitmap.c

    ra93d79a r8fb1bf82  
    3232/**
    3333 * @file
    34  * @brief       Implementation of bitmap ADT.
     34 * @brief Implementation of bitmap ADT.
    3535 *
    3636 * This file implements bitmap ADT and provides functions for
    … …  
    5151 * No portion of the bitmap is set or cleared by this function.
    5252 *
    53  * @param bitmap Bitmap structure.
    54  * @param map Address of the memory used to hold the map.
    55  * @param bits Number of bits stored in bitmap.
     53 * @param bitmap        Bitmap structure.
     54 * @param map           Address of the memory used to hold the map.
     55 * @param bits          Number of bits stored in bitmap.
    5656 */
    5757void bitmap_initialize(bitmap_t *bitmap, uint8_t *map, size_t bits)
    … …  
    6363/** Set range of bits.
    6464 *
    65  * @param bitmap Bitmap structure.
    66  * @param start Starting bit.
    67  * @param bits Number of bits to set.
     65 * @param bitmap        Bitmap structure.
     66 * @param start         Starting bit.
     67 * @param bits          Number of bits to set.
    6868 */
    6969void bitmap_set_range(bitmap_t *bitmap, size_t start, size_t bits)
    … …  
    7171        size_t i = 0;
    7272        size_t aligned_start;
    73         size_t lub;             /* leading unaligned bits */
    74         size_t amb;             /* aligned middle bits */
    75         size_t tab;             /* trailing aligned bits */
     73        size_t lub;     /* leading unaligned bits */
     74        size_t amb;     /* aligned middle bits */
     75        size_t tab;     /* trailing aligned bits */
    7676       
    7777        ASSERT(start + bits <= bitmap->bits);
    … …  
    8282        tab = amb % 8;
    8383       
    84         if ( start + bits < aligned_start ) {
    85             /*
    86             * Set bits in the middle of byte
    87             */
    88             bitmap->map[start / 8] |= ((1 << lub)-1) << (start&7);
    89             return;
     84        if (!bits)
     85                return;
     86
     87        if (start + bits < aligned_start) {
     88                /* Set bits in the middle of byte. */
     89                bitmap->map[start / 8] |= ((1 << lub) - 1) << (start & 7);
     90                return;
    9091        }
    9192       
    9293        if (lub) {
    93                 /*
    94                  * Make sure to set any leading unaligned bits.
    95                  */
     94                /* Make sure to set any leading unaligned bits. */
    9695                bitmap->map[start / 8] |= ~((1 << (8 - lub)) - 1);
    9796        }
    9897        for (i = 0; i < amb / 8; i++) {
    99                 /*
    100                  * The middle bits can be set byte by byte.
    101                  */
     98                /* The middle bits can be set byte by byte. */
    10299                bitmap->map[aligned_start / 8 + i] = ALL_ONES;
    103100        }
    104101        if (tab) {
    105                 /*
    106                  * Make sure to set any trailing aligned bits.
    107                  */
     102                /* Make sure to set any trailing aligned bits. */
    108103                bitmap->map[aligned_start / 8 + i] |= (1 << tab) - 1;
    109104        }
    … …  
    113108/** Clear range of bits.
    114109 *
    115  * @param bitmap Bitmap structure.
    116  * @param start Starting bit.
    117  * @param bits Number of bits to clear.
     110 * @param bitmap        Bitmap structure.
     111 * @param start         Starting bit.
     112 * @param bits          Number of bits to clear.
    118113 */
    119114void bitmap_clear_range(bitmap_t *bitmap, size_t start, size_t bits)
    … …  
    121116        size_t i = 0;
    122117        size_t aligned_start;
    123         size_t lub;             /* leading unaligned bits */
    124         size_t amb;             /* aligned middle bits */
    125         size_t tab;             /* trailing aligned bits */
     118        size_t lub;     /* leading unaligned bits */
     119        size_t amb;     /* aligned middle bits */
     120        size_t tab;     /* trailing aligned bits */
    126121       
    127122        ASSERT(start + bits <= bitmap->bits);
    … …  
    132127        tab = amb % 8;
    133128
    134         if ( start + bits < aligned_start )
    135         {
    136             /*
    137             * Set bits in the middle of byte
    138             */
    139             bitmap->map[start / 8] &= ~(((1 << lub)-1) << (start&7));
    140             return;
     129        if (!bits)
     130                return;
     131
     132        if (start + bits < aligned_start) {
     133                /* Set bits in the middle of byte */
     134                bitmap->map[start / 8] &= ~(((1 << lub) - 1) << (start & 7));
     135                return;
    141136        }
    142137
    143 
    144138        if (lub) {
    145                 /*
    146                  * Make sure to clear any leading unaligned bits.
    147                  */
     139                /* Make sure to clear any leading unaligned bits. */
    148140                bitmap->map[start / 8] &= (1 << (8 - lub)) - 1;
    149141        }
    150142        for (i = 0; i < amb / 8; i++) {
    151                 /*
    152                  * The middle bits can be cleared byte by byte.
    153                  */
     143                /* The middle bits can be cleared byte by byte. */
    154144                bitmap->map[aligned_start / 8 + i] = ALL_ZEROES;
    155145        }
    156146        if (tab) {
    157                 /*
    158                  * Make sure to clear any trailing aligned bits.
    159                  */
     147                /* Make sure to clear any trailing aligned bits. */
    160148                bitmap->map[aligned_start / 8 + i] &= ~((1 << tab) - 1);
    161149        }
    … …  
    165153/** Copy portion of one bitmap into another bitmap.
    166154 *
    167  * @param dst Destination bitmap.
    168  * @param src Source bitmap.
    169  * @param bits Number of bits to copy.
     155 * @param dst           Destination bitmap.
     156 * @param src           Source bitmap.
     157 * @param bits          Number of bits to copy.
    170158 */
    171159void bitmap_copy(bitmap_t *dst, bitmap_t *src, size_t bits)

  • kernel/generic/src/adt/btree.c

    ra93d79a r8fb1bf82  
    888888                *leaf_node = cur;
    889889               
     890                if (cur->keys == 0)
     891                        return NULL;
     892
    890893                /*
    891894                 * The key can be in the leftmost subtree.
    … …  
    926929                                return key == cur->key[i - 1] ? val : NULL;
    927930                }
    928                 descend:
     931descend:
    929932                ;
    930933        }

  • kernel/generic/src/ddi/ddi.c

    ra93d79a r8fb1bf82  
    258258}
    259259
     260/** Disable or enable specified interrupts.
     261 *
     262 * @param irq the interrupt to be enabled/disabled.
     263 * @param enable if true enable the interrupt, disable otherwise.
     264 *
     265 * @retutn Zero on success, error code otherwise.
     266 */
     267unative_t sys_interrupt_enable(int irq, int enable)
     268{
     269/* FIXME: this needs to be generic code, or better not be in kernel at all. */
     270#if 0
     271        cap_t task_cap = cap_get(TASK);
     272        if (!(task_cap & CAP_IRQ_REG))
     273                return EPERM;
     274               
     275        if (irq < 0 || irq > 16) {
     276                return EINVAL;
     277        }
     278       
     279        uint16_t irq_mask = (uint16_t)(1 << irq);
     280        if (enable) {
     281                trap_virtual_enable_irqs(irq_mask);
     282        } else {
     283                trap_virtual_disable_irqs(irq_mask);
     284        }
     285       
     286#endif
     287        return 0;
     288}
     289
    260290/** @}
    261291 */

  • kernel/generic/src/ipc/kbox.c

    ra93d79a r8fb1bf82  
    107107                /* Terminate debugging session (if any). */
    108108                LOG("Terminate debugging session.");
    109                 irq_spinlock_lock(&TASK->lock, true);
     109                mutex_lock(&TASK->udebug.lock);
    110110                udebug_task_cleanup(TASK);
    111                 irq_spinlock_unlock(&TASK->lock, true);
     111                mutex_unlock(&TASK->udebug.lock);
    112112        } else {
    113113                LOG("Was not debugger.");

  • kernel/generic/src/main/main.c

    ra93d79a r8fb1bf82  
    9797/** Boot allocations. */
    9898ballocs_t ballocs = {
    99         .base = NULL,
     99        .base = (uintptr_t) NULL,
    100100        .size = 0
    101101};

  • kernel/generic/src/mm/as.c

    ra93d79a r8fb1bf82  
    312312         *
    313313         */
    314         if (overlaps(va, size, NULL, PAGE_SIZE))
     314        if (overlaps(va, size, (uintptr_t) NULL, PAGE_SIZE))
    315315                return false;
    316316       

  • kernel/generic/src/mm/frame.c

    ra93d79a r8fb1bf82  
    878878                 * the assert
    879879                 */
    880                 ASSERT(confframe != NULL);
     880                ASSERT(confframe != ADDR2PFN((uintptr_t ) NULL));
    881881               
    882882                /* If confframe is supposed to be inside our zone, then make sure
    … …  
    11041104         */
    11051105        pfn_t pfn = ADDR2PFN(frame);
    1106         size_t znum = find_zone(pfn, 1, NULL);
     1106        size_t znum = find_zone(pfn, 1, 0);
    11071107       
    11081108        ASSERT(znum != (size_t) -1);
    … …  
    11411141         * First, find host frame zone for addr.
    11421142         */
    1143         size_t znum = find_zone(pfn, 1, NULL);
     1143        size_t znum = find_zone(pfn, 1, 0);
    11441144       
    11451145        ASSERT(znum != (size_t) -1);

  • kernel/generic/src/synch/smc.c

    ra93d79a r8fb1bf82  
    4444unative_t sys_smc_coherence(uintptr_t va, size_t size)
    4545{
    46         if (overlaps(va, size, NULL, PAGE_SIZE))
     46        if (overlaps(va, size, (uintptr_t) NULL, PAGE_SIZE))
    4747                return EINVAL;
    4848

  • kernel/generic/src/syscall/copy.c

    ra93d79a r8fb1bf82  
    6868        if (!KERNEL_ADDRESS_SPACE_SHADOWED) {
    6969                if (overlaps((uintptr_t) uspace_src, size,
    70                         KERNEL_ADDRESS_SPACE_START, KERNEL_ADDRESS_SPACE_END-KERNEL_ADDRESS_SPACE_START)) {
     70                        KERNEL_ADDRESS_SPACE_START,
     71                        KERNEL_ADDRESS_SPACE_END - KERNEL_ADDRESS_SPACE_START)) {
    7172                        /*
    7273                         * The userspace source block conflicts with kernel address space.
    … …  
    7576                }
    7677        }
     78
     79#ifdef ADDRESS_SPACE_HOLE_START
     80        /*
     81         * Check whether the address is outside the address space hole.
     82         */
     83        if (overlaps((uintptr_t) uspace_src, size, ADDRESS_SPACE_HOLE_START,
     84            ADDRESS_SPACE_HOLE_END - ADDRESS_SPACE_HOLE_START))
     85                return EPERM;
     86#endif
    7787       
    7888        ipl = interrupts_disable();
    … …  
    109119        if (!KERNEL_ADDRESS_SPACE_SHADOWED) {
    110120                if (overlaps((uintptr_t) uspace_dst, size,
    111                         KERNEL_ADDRESS_SPACE_START, KERNEL_ADDRESS_SPACE_END-KERNEL_ADDRESS_SPACE_START)) {
     121                        KERNEL_ADDRESS_SPACE_START,
     122                        KERNEL_ADDRESS_SPACE_END - KERNEL_ADDRESS_SPACE_START)) {
    112123                        /*
    113124                         * The userspace destination block conflicts with kernel address space.
    … …  
    116127                }
    117128        }
     129
     130#ifdef ADDRESS_SPACE_HOLE_START
     131        /*
     132         * Check whether the address is outside the address space hole.
     133         */
     134        if (overlaps((uintptr_t) uspace_dst, size, ADDRESS_SPACE_HOLE_START,
     135            ADDRESS_SPACE_HOLE_END - ADDRESS_SPACE_HOLE_START))
     136                return EPERM;
     137#endif
    118138       
    119139        ipl = interrupts_disable();

  • kernel/generic/src/syscall/syscall.c

    ra93d79a r8fb1bf82  
    159159        (syshandler_t) sys_physmem_map,
    160160        (syshandler_t) sys_iospace_enable,
     161        (syshandler_t) sys_interrupt_enable,
    161162       
    162163        /* Sysinfo syscalls */

  • kernel/generic/src/udebug/udebug_ops.c

    ra93d79a r8fb1bf82  
    428428 * @param data_size Place to store size of the data.
    429429 *
    430  * @returns EOK.
     430 * @return EOK.
    431431 *
    432432 */

  • kernel/tools/amd64/decpt.py

    ra93d79a r8fb1bf82  
    77def main():
    88    if len(sys.argv) != 2 or not sys.argv[1].startswith('0x'):
    9         print "%s 0x..." % sys.argv[0]
     9        print("%s 0x..." % sys.argv[0])
    1010        sys.exit(1)
    1111   
    … …  
    1616    ptl1 = (address >> 30) & 0x1ff
    1717    ptl0 = (address >> 39) & 0x1ff
    18     print "Ptl0:   %3d" % ptl0
    19     print "Ptl1:   %3d" % ptl1
    20     print "Ptl2:   %3d" % ptl2
    21     print "Ptl3:   %3d" % ptl3
    22     print "Offset: 0x%x" % offset
     18    print("Ptl0:   %3d" % ptl0)
     19    print("Ptl1:   %3d" % ptl1)
     20    print("Ptl2:   %3d" % ptl2)
     21    print("Ptl3:   %3d" % ptl3)
     22    print("Offset: 0x%x" % offset)
    2323
    2424if __name__ == '__main__':

  • kernel/tools/genmap.py

    ra93d79a r8fb1bf82  
    8686        obdump = read_obdump(obmapf)
    8787       
    88         def sorter(x,y):
    89                 return cmp(x[0],y[0])
     88        def key_sorter(x):
     89                return x[0]
    9090       
    9191        for line in kmapf:
    … …  
    9393                res = startfile.match(line)
    9494               
    95                 if ((res) and (obdump[res.group(1)].has_key(res.group(3)))):
     95                if ((res) and (res.group(3) in obdump[res.group(1)])):
    9696                        offset = int(res.group(2), 16)
    9797                        fname = res.group(3)
    9898                        symbols = obdump[res.group(1)][fname]
    99                         symbols.sort(sorter)
     99                        symbols.sort(key = key_sorter)
    100100                        for addr, symbol in symbols:
    101101                                value = fname + ':' + symbol
    … …  
    107107def main():
    108108        if (len(sys.argv) != 4):
    109                 print "Usage: %s <kernel.map> <nm dump> <output.bin>" % sys.argv[0]
     109                print("Usage: %s <kernel.map> <nm dump> <output.bin>" % sys.argv[0])
    110110                return 1
    111111       
    112112        kmapf = open(sys.argv[1], 'r')
    113113        obmapf = open(sys.argv[2], 'r')
    114         out = open(sys.argv[3], 'w')
     114        out = open(sys.argv[3], 'wb')
    115115       
    116116        generate(kmapf, obmapf, out)

  • kernel/tools/ia32/decpt.py

    ra93d79a r8fb1bf82  
    77def main():
    88    if len(sys.argv) != 2 or not sys.argv[1].startswith('0x'):
    9         print "%s 0x..." % sys.argv[0]
     9        print("%s 0x..." % sys.argv[0])
    1010        sys.exit(1)
    1111   
    … …  
    1414    ptl1 = (address >> 12) & 0x3ff
    1515    ptl0 = (address >> 22) & 0x3ff
    16     print "Ptl0:   %3d" % ptl0
    17     print "Ptl1:   %3d" % ptl1
    18     print "Offset: 0x%x" % offset
     16    print("Ptl0:   %3d" % ptl0)
     17    print("Ptl1:   %3d" % ptl1)
     18    print("Offset: 0x%x" % offset)
    1919
    2020if __name__ == '__main__':
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