source: mainline/kernel/arch/amd64/include/interrupt.h@ c0e9f3f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c0e9f3f was c0e9f3f, checked in by Jakub Jermar <jakub@…>, 15 years ago

Change the amd64 istate_t and interrupt handler macro so that the istate
structure now captures all GPRs and provides seamless stack frame linkage.

  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup amd64interrupt
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_amd64_INTERRUPT_H_
36#define KERN_amd64_INTERRUPT_H_
37
38#include <typedefs.h>
39#include <arch/pm.h>
40#include <trace.h>
41
42#define IVT_ITEMS IDT_ITEMS
43#define IVT_FIRST 0
44
45#define EXC_COUNT 32
46#define IRQ_COUNT 16
47
48#define IVT_EXCBASE 0
49#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT)
50#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT)
51
52#define IRQ_CLK 0
53#define IRQ_KBD 1
54#define IRQ_PIC1 2
55#define IRQ_PIC_SPUR 7
56#define IRQ_MOUSE 12
57#define IRQ_DP8390 9
58
59/* This one must have four least significant bits set to ones */
60#define VECTOR_APIC_SPUR (IVT_ITEMS - 1)
61
62#if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
63#error Wrong definition of VECTOR_APIC_SPUR
64#endif
65
66#define VECTOR_DEBUG 1
67#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK)
68#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR)
69#define VECTOR_SYSCALL IVT_FREEBASE
70#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1)
71#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2)
72
73/** This is passed to interrupt handlers */
74typedef struct istate {
75 uint64_t rax;
76 uint64_t rbx;
77 uint64_t rcx;
78 uint64_t rdx;
79 uint64_t rsi;
80 uint64_t rdi;
81 uint64_t rbp;
82 uint64_t r8;
83 uint64_t r9;
84 uint64_t r10;
85 uint64_t r11;
86 uint64_t r12;
87 uint64_t r13;
88 uint64_t r14;
89 uint64_t r15;
90 uint64_t alignment; /* align rbp_frame on multiple of 16 */
91 uint64_t rbp_frame; /* imitation of frame pointer linkage */
92 uint64_t rip_frame; /* imitation of return address linkage */
93 uint64_t error_word; /* real or fake error word */
94 uint64_t rip;
95 uint64_t cs;
96 uint64_t rflags;
97 uint64_t rsp; /* only if istate_t is from uspace */
98 uint64_t ss; /* only if istate_t is from uspace */
99} istate_t;
100
101/** Return true if exception happened while in userspace */
102NO_TRACE static inline int istate_from_uspace(istate_t *istate)
103{
104 return !(istate->rip & 0x8000000000000000);
105}
106
107NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
108 uintptr_t retaddr)
109{
110 istate->rip = retaddr;
111}
112
113NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
114{
115 return istate->rip;
116}
117
118NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
119{
120 return istate->rbp;
121}
122
123extern void (* disable_irqs_function)(uint16_t);
124extern void (* enable_irqs_function)(uint16_t);
125extern void (* eoi_function)(void);
126
127extern void interrupt_init(void);
128extern void trap_virtual_enable_irqs(uint16_t);
129extern void trap_virtual_disable_irqs(uint16_t);
130
131#endif
132
133/** @}
134 */
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