Changeset 5f70118 in mainline for kernel/arch
- Timestamp:
- 2010-01-10T12:16:59Z (16 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- c77a64f
- Parents:
- 309ede1 (diff), 1ac3a52 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - Location:
- kernel/arch
- Files:
-
- 12 added
- 2 deleted
- 70 edited
- 4 moved
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amd64/Makefile.inc (modified) (2 diffs)
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amd64/_link.ld.in (modified) (1 diff)
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amd64/include/context.h (modified) (1 diff)
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amd64/include/interrupt.h (modified) (3 diffs)
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amd64/include/mm/page.h (modified) (1 diff)
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amd64/include/types.h (modified) (1 diff)
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amd64/src/amd64.c (modified) (3 diffs)
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amd64/src/asm_utils.S (modified) (5 diffs)
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amd64/src/boot/boot.S (modified) (2 diffs)
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amd64/src/cpu/cpu.c (modified) (2 diffs)
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amd64/src/debug/stacktrace.c (added)
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amd64/src/debug/stacktrace_asm.S (added)
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amd64/src/interrupt.c (modified) (4 diffs)
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amd64/src/mm/page.c (modified) (1 diff)
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amd64/src/smp/ap.S (modified) (1 diff)
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arm32/Makefile.inc (modified) (1 diff)
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arm32/_link.ld.in (modified) (1 diff)
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arm32/include/atomic.h (modified) (2 diffs)
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arm32/include/exception.h (modified) (2 diffs)
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arm32/include/mm/as.h (modified) (1 diff)
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arm32/include/mm/page.h (modified) (10 diffs)
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arm32/include/ras.h (added)
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arm32/include/types.h (modified) (1 diff)
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arm32/src/arm32.c (modified) (3 diffs)
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arm32/src/debug/stacktrace.c (moved) (moved from kernel/arch/mips32/include/arg.h ) (3 diffs)
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arm32/src/debug/stacktrace_asm.S (added)
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arm32/src/exc_handler.S (modified) (7 diffs)
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arm32/src/mm/as.c (modified) (2 diffs)
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arm32/src/mm/page.c (modified) (1 diff)
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arm32/src/ras.c (added)
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arm32/src/userspace.c (modified) (2 diffs)
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ia32/Makefile.inc (modified) (3 diffs)
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ia32/_link.ld.in (modified) (1 diff)
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ia32/include/context.h (modified) (1 diff)
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ia32/include/cpu.h (modified) (2 diffs)
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ia32/include/cpuid.h (modified) (1 diff)
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ia32/include/interrupt.h (modified) (2 diffs)
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ia32/include/mm/page.h (modified) (1 diff)
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ia32/include/types.h (modified) (1 diff)
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ia32/src/asm.S (modified) (3 diffs)
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ia32/src/boot/boot.S (modified) (3 diffs)
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ia32/src/cpu/cpu.c (modified) (5 diffs)
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ia32/src/debug/stacktrace.c (moved) (moved from uspace/lib/libc/arch/mips32/include/stackarg.h ) (2 diffs)
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ia32/src/debug/stacktrace_asm.S (added)
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ia32/src/ia32.c (modified) (3 diffs)
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ia32/src/interrupt.c (modified) (4 diffs)
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ia32/src/mm/page.c (modified) (1 diff)
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ia32/src/proc/scheduler.c (modified) (1 diff)
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ia32/src/smp/ap.S (modified) (1 diff)
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ia32/src/userspace.c (modified) (1 diff)
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ia64/Makefile.inc (modified) (1 diff)
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ia64/_link.ld.in (modified) (4 diffs)
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ia64/include/asm.h (modified) (1 diff)
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ia64/include/interrupt.h (modified) (2 diffs)
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ia64/src/cpu/cpu.c (modified) (1 diff)
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ia64/src/debug/stacktrace.c (moved) (moved from kernel/generic/include/stackarg.h ) (3 diffs)
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ia64/src/debug/stacktrace_asm.S (added)
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ia64/src/ivt.S (modified) (1 diff)
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ia64/src/mm/as.c (modified) (1 diff)
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ia64/src/start.S (modified) (1 diff)
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mips32/Makefile.inc (modified) (1 diff)
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mips32/_link.ld.in (modified) (1 diff)
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mips32/include/exception.h (modified) (2 diffs)
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mips32/include/mm/page.h (modified) (1 diff)
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mips32/include/types.h (modified) (1 diff)
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mips32/src/debug/stacktrace.c (moved) (moved from uspace/lib/libc/arch/ia32/include/stackarg.h ) (3 diffs)
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mips32/src/debug/stacktrace_asm.S (added)
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ppc32/Makefile.inc (modified) (1 diff)
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ppc32/_link.ld.in (modified) (1 diff)
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ppc32/include/arg.h (deleted)
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ppc32/include/exception.h (modified) (2 diffs)
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ppc32/include/mm/page.h (modified) (1 diff)
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ppc32/include/types.h (modified) (1 diff)
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ppc32/src/debug/stacktrace.c (added)
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ppc32/src/debug/stacktrace_asm.S (added)
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ppc32/src/mm/as.c (modified) (1 diff)
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ppc32/src/mm/page.c (modified) (1 diff)
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ppc32/src/mm/tlb.c (modified) (1 diff)
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ppc32/src/ppc32.c (modified) (1 diff)
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sparc64/Makefile.inc (modified) (1 diff)
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sparc64/_link.ld.in (modified) (1 diff)
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sparc64/include/arg.h (deleted)
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sparc64/include/interrupt.h (modified) (2 diffs)
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sparc64/src/context.S (modified) (3 diffs)
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sparc64/src/debug/stacktrace.c (added)
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sparc64/src/debug/stacktrace_asm.S (added)
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sparc64/src/mm/tlb.c (modified) (1 diff)
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sparc64/src/trap/trap_table.S (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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kernel/arch/amd64/Makefile.inc
r309ede1 r5f70118 34 34 BFD = binary 35 35 TARGET = amd64-linux-gnu 36 CLANG_ARCH = x86_64 36 37 TOOLCHAIN_DIR = $(CROSS_PREFIX)/amd64 37 38 38 39 FPU_NO_CFLAGS = -mno-sse -mno-sse2 39 CMN1 = -m64 -mcmodel=kernel -mno-red-zone -fno-unwind-tables 40 CMN1 = -m64 -mcmodel=kernel -mno-red-zone -fno-unwind-tables -fno-omit-frame-pointer 40 41 GCC_CFLAGS += $(CMN1) 41 42 ICC_CFLAGS += $(CMN1) … … 59 60 arch/$(KARCH)/src/boot/boot.S \ 60 61 arch/$(KARCH)/src/boot/memmap.c \ 62 arch/$(KARCH)/src/debug/stacktrace.c \ 63 arch/$(KARCH)/src/debug/stacktrace_asm.S \ 61 64 arch/$(KARCH)/src/pm.c \ 62 65 arch/$(KARCH)/src/context.S \ -
kernel/arch/amd64/_link.ld.in
r309ede1 r5f70118 44 44 *(COMMON); /* global variables */ 45 45 46 . = ALIGN(8); 46 47 symbol_table = .; 47 48 *(symtab.*); /* Symbol table, must be LAST symbol!*/ -
kernel/arch/amd64/include/context.h
r309ede1 r5f70118 46 46 #define SP_DELTA 16 47 47 48 #define context_set(c, _pc, stack, size) \ 49 do { \ 50 (c)->pc = (uintptr_t) (_pc); \ 51 (c)->sp = ((uintptr_t) (stack)) + (size) - SP_DELTA; \ 52 (c)->rbp = 0; \ 53 } while (0) 54 48 55 #endif /* KERNEL */ 49 56 -
kernel/arch/amd64/include/interrupt.h
r309ede1 r5f70118 70 70 71 71 /** This is passed to interrupt handlers */ 72 typedef struct {72 typedef struct istate { 73 73 uint64_t rax; 74 74 uint64_t rcx; … … 80 80 uint64_t r10; 81 81 uint64_t r11; 82 uint64_t rbp; 82 83 uint64_t error_word; 83 84 uint64_t rip; … … 101 102 return istate->rip; 102 103 } 104 static inline unative_t istate_get_fp(istate_t *istate) 105 { 106 return istate->rbp; 107 } 103 108 104 109 extern void (* disable_irqs_function)(uint16_t irqmask); -
kernel/arch/amd64/include/mm/page.h
r309ede1 r5f70118 177 177 #define PFERR_CODE_ID (1 << 4) 178 178 179 static inline int get_pt_flags(pte_t *pt, size_t i) 179 /** Page Table Entry. */ 180 typedef struct { 181 unsigned present : 1; 182 unsigned writeable : 1; 183 unsigned uaccessible : 1; 184 unsigned page_write_through : 1; 185 unsigned page_cache_disable : 1; 186 unsigned accessed : 1; 187 unsigned dirty : 1; 188 unsigned unused: 1; 189 unsigned global : 1; 190 unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */ 191 unsigned avl : 2; 192 unsigned addr_12_31 : 30; 193 unsigned addr_32_51 : 21; 194 unsigned no_execute : 1; 195 } __attribute__ ((packed)) pte_t; 196 197 static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 180 198 { 181 199 pte_t *p = &pt[i]; -
kernel/arch/amd64/include/types.h
r309ede1 r5f70118 82 82 #define PRIxn "llx" 83 83 84 /** Page Table Entry. */85 typedef struct {86 unsigned present : 1;87 unsigned writeable : 1;88 unsigned uaccessible : 1;89 unsigned page_write_through : 1;90 unsigned page_cache_disable : 1;91 unsigned accessed : 1;92 unsigned dirty : 1;93 unsigned unused: 1;94 unsigned global : 1;95 unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */96 unsigned avl : 2;97 unsigned addr_12_31 : 30;98 unsigned addr_32_51 : 21;99 unsigned no_execute : 1;100 } __attribute__ ((packed)) pte_t;101 102 84 #endif 103 85 -
kernel/arch/amd64/src/amd64.c
r309ede1 r5f70118 67 67 #include <ddi/irq.h> 68 68 #include <sysinfo/sysinfo.h> 69 #include <memstr.h> 69 70 70 71 /** Disable I/O on non-privileged levels … … 211 212 i8042_wire(i8042_instance, kbrd); 212 213 trap_virtual_enable_irqs(1 << IRQ_KBD); 214 trap_virtual_enable_irqs(1 << IRQ_MOUSE); 213 215 } 214 216 } … … 218 220 * self-sufficient. 219 221 */ 220 sysinfo_set_item_val("kbd", NULL, true); 221 sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD); 222 sysinfo_set_item_val("kbd.address.physical", NULL, 222 sysinfo_set_item_val("i8042", NULL, true); 223 sysinfo_set_item_val("i8042.inr_a", NULL, IRQ_KBD); 224 sysinfo_set_item_val("i8042.inr_b", NULL, IRQ_MOUSE); 225 sysinfo_set_item_val("i8042.address.physical", NULL, 223 226 (uintptr_t) I8042_BASE); 224 sysinfo_set_item_val(" kbd.address.kernel", NULL,227 sysinfo_set_item_val("i8042.address.kernel", NULL, 225 228 (uintptr_t) I8042_BASE); 226 229 #endif -
kernel/arch/amd64/src/asm_utils.S
r309ede1 r5f70118 27 27 # 28 28 29 #define IREGISTER_SPACE 7229 #define IREGISTER_SPACE 80 30 30 31 31 #define IOFFSET_RAX 0x0 … … 38 38 #define IOFFSET_R10 0x38 39 39 #define IOFFSET_R11 0x40 40 #define IOFFSET_RBP 0x48 40 41 41 42 # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word … … 179 180 movq %r10, IOFFSET_R10(%rsp) 180 181 movq %r11, IOFFSET_R11(%rsp) 182 movq %rbp, IOFFSET_RBP(%rsp) 181 183 .endm 182 184 … … 191 193 movq IOFFSET_R10(%rsp), %r10 192 194 movq IOFFSET_R11(%rsp), %r11 195 movq IOFFSET_RBP(%rsp), %rbp 193 196 .endm 194 197 … … 235 238 cld 236 239 240 # Stop stack traces here 241 xorq %rbp, %rbp 242 237 243 movq $(\i), %rdi # %rdi - first parameter 238 244 movq %rsp, %rsi # %rsi - pointer to istate -
kernel/arch/amd64/src/boot/boot.S
r309ede1 r5f70118 174 174 call arch_pre_main 175 175 176 # create the first stack frame 177 pushq $0 178 movq %rsp, %rbp 179 176 180 call main_bsp 177 181 … … 329 333 330 334 extended_cpuid_msg: 331 .asciz "E xtended CPUID not supported. System halted."335 .asciz "Error: Extended CPUID not supported -- CPU is not 64-bit. System halted." 332 336 long_mode_msg: 333 .asciz " 64bit long mode not supported. System halted."337 .asciz "Error: 64-bit long mode not supported. System halted." 334 338 noexecute_msg: 335 .asciz " No-execute pages not supported. System halted."339 .asciz "Error: No-execute pages not supported. System halted." 336 340 fx_msg: 337 .asciz " FXSAVE/FXRESTORE instructions not supported. System halted."341 .asciz "Error: FXSAVE/FXRESTORE instructions not supported. System halted." 338 342 sse2_msg: 339 .asciz " SSE2 instructions not supported. System halted."343 .asciz "Error: SSE2 instructions not supported. System halted." -
kernel/arch/amd64/src/cpu/cpu.c
r309ede1 r5f70118 130 130 CPU->arch.vendor = VendorUnknown; 131 131 if (has_cpuid()) { 132 cpuid( 0, &info);132 cpuid(INTEL_CPUID_LEVEL, &info); 133 133 134 134 /* … … 150 150 } 151 151 152 cpuid( 1, &info);152 cpuid(INTEL_CPUID_STANDARD, &info); 153 153 CPU->arch.family = (info.cpuid_eax >> 8) & 0xf; 154 154 CPU->arch.model = (info.cpuid_eax >> 4) & 0xf; -
kernel/arch/amd64/src/interrupt.c
r309ede1 r5f70118 53 53 #include <ddi/irq.h> 54 54 #include <symtab.h> 55 #include <stacktrace.h> 55 56 56 57 /* … … 80 81 istate->r10, istate->r11); 81 82 printf("%%rsp=%#llx\n", &istate->stack[0]); 83 84 stack_trace_istate(istate); 82 85 } 83 86 … … 96 99 decode_istate(n, istate); 97 100 panic("Unserviced interrupt."); 101 } 102 103 static void de_fault(int n, istate_t *istate) 104 { 105 fault_if_from_uspace(istate, "Divide error."); 106 decode_istate(n, istate); 107 panic("Divide error."); 98 108 } 99 109 … … 200 210 } 201 211 212 exc_register(0, "de_fault", (iroutine) de_fault); 202 213 exc_register(7, "nm_fault", (iroutine) nm_fault); 203 214 exc_register(12, "ss_fault", (iroutine) ss_fault); -
kernel/arch/amd64/src/mm/page.c
r309ede1 r5f70118 203 203 { 204 204 if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) 205 panic("Unable to map physical memory %p (%d bytes).", physaddr, size) 205 panic("Unable to map physical memory %p (%d bytes).", physaddr, 206 size); 206 207 207 208 uintptr_t virtaddr = PA2KA(last_frame); -
kernel/arch/amd64/src/smp/ap.S
r309ede1 r5f70118 99 99 start64: 100 100 movq (ctx), %rsp 101 pushq $0 102 movq %rsp, %rbp 101 103 call main_ap - AP_BOOT_OFFSET + BOOT_OFFSET # never returns 102 104 -
kernel/arch/arm32/Makefile.inc
r309ede1 r5f70118 57 57 arch/$(KARCH)/src/exception.c \ 58 58 arch/$(KARCH)/src/userspace.c \ 59 arch/$(KARCH)/src/debug/stacktrace.c \ 60 arch/$(KARCH)/src/debug/stacktrace_asm.S \ 59 61 arch/$(KARCH)/src/mm/as.c \ 60 62 arch/$(KARCH)/src/mm/frame.c \ 61 63 arch/$(KARCH)/src/mm/page.c \ 62 64 arch/$(KARCH)/src/mm/tlb.c \ 63 arch/$(KARCH)/src/mm/page_fault.c 65 arch/$(KARCH)/src/mm/page_fault.c \ 66 arch/$(KARCH)/src/ras.c 64 67 65 68 ifeq ($(MACHINE),testarm) -
kernel/arch/arm32/_link.ld.in
r309ede1 r5f70118 34 34 *(.sdata); 35 35 *(.reginfo); 36 . = ALIGN(8); 36 37 symbol_table = .; 37 38 *(symtab.*); -
kernel/arch/arm32/include/atomic.h
r309ede1 r5f70118 37 37 #define KERN_arm32_ATOMIC_H_ 38 38 39 #include <arch/asm.h> 40 39 41 /** Atomic addition. 40 42 * … … 47 49 static inline long atomic_add(atomic_t *val, int i) 48 50 { 49 int ret; 50 volatile long *mem = &(val->count); 51 52 asm volatile ( 53 "1:\n" 54 "ldr r2, [%[mem]]\n" 55 "add r3, r2, %[i]\n" 56 "str r3, %[ret]\n" 57 "swp r3, r3, [%[mem]]\n" 58 "cmp r3, r2\n" 59 "bne 1b\n" 60 : [ret] "=m" (ret) 61 : [mem] "r" (mem), [i] "r" (i) 62 : "r3", "r2" 63 ); 51 long ret; 52 53 /* 54 * This implementation is for UP pre-ARMv6 systems where we do not have 55 * the LDREX and STREX instructions. 56 */ 57 ipl_t ipl = interrupts_disable(); 58 val->count += i; 59 ret = val->count; 60 interrupts_restore(ipl); 64 61 65 62 return ret; -
kernel/arch/arm32/include/exception.h
r309ede1 r5f70118 86 86 87 87 /** Struct representing CPU state saved when an exception occurs. */ 88 typedef struct {88 typedef struct istate { 89 89 uint32_t spsr; 90 90 uint32_t sp; … … 133 133 } 134 134 135 static inline unative_t istate_get_fp(istate_t *istate) 136 { 137 return istate->r11; 138 } 139 135 140 136 141 extern void install_exception_handlers(void); -
kernel/arch/arm32/include/mm/as.h
r309ede1 r5f70118 54 54 #define as_destructor_arch(as) (as != as) 55 55 #define as_create_arch(as, flags) (as != as) 56 #define as_install_arch(as)57 56 #define as_deinstall_arch(as) 58 57 #define as_invalidate_translation_cache(as, page, cnt) -
kernel/arch/arm32/include/mm/page.h
r309ede1 r5f70118 75 75 /* Get PTE address accessors for each level. */ 76 76 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ 77 ((pte_t *) ((((pte_ level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))77 ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) 78 78 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ 79 79 (ptl1) … … 81 81 (ptl2) 82 82 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ 83 ((uintptr_t) ((((pte_ level1_t *)(ptl3))[(i)]).frame_base_addr << 12))83 ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) 84 84 85 85 /* Set PTE address accessors for each level. */ 86 86 #define SET_PTL0_ADDRESS_ARCH(ptl0) \ 87 (set_ptl0_addr((pte_ level0_t *) (ptl0)))87 (set_ptl0_addr((pte_t *) (ptl0))) 88 88 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ 89 (((pte_ level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10)89 (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) 90 90 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) 91 91 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) 92 92 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ 93 (((pte_ level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)93 (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) 94 94 95 95 /* Get PTE flags accessors for each level. */ 96 96 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ 97 get_pt_level0_flags((pte_ level0_t *) (ptl0), (size_t) (i))97 get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) 98 98 #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ 99 99 PAGE_PRESENT … … 101 101 PAGE_PRESENT 102 102 #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ 103 get_pt_level1_flags((pte_ level1_t *) (ptl3), (size_t) (i))103 get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) 104 104 105 105 /* Set PTE flags accessors for each level. */ 106 106 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ 107 set_pt_level0_flags((pte_ level0_t *) (ptl0), (size_t) (i), (x))107 set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) 108 108 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) 109 109 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) 110 110 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ 111 set_pt_level1_flags((pte_ level1_t *) (ptl3), (size_t) (i), (x))111 set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x)) 112 112 113 113 /* Macros for querying the last-level PTE entries. */ … … 115 115 (*((uint32_t *) (pte)) != 0) 116 116 #define PTE_PRESENT_ARCH(pte) \ 117 (((pte_ level0_t *) (pte))->descriptor_type != 0)117 (((pte_t *) (pte))->l0.descriptor_type != 0) 118 118 #define PTE_GET_FRAME_ARCH(pte) \ 119 (((pte_ level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)119 (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) 120 120 #define PTE_WRITABLE_ARCH(pte) \ 121 (((pte_level1_t *) (pte))->access_permission_0 == \ 122 PTE_AP_USER_RW_KERNEL_RW) 121 (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) 123 122 #define PTE_EXECUTABLE_ARCH(pte) \ 124 123 1 … … 159 158 } ATTRIBUTE_PACKED pte_level1_t; 160 159 160 typedef union { 161 pte_level0_t l0; 162 pte_level1_t l1; 163 } pte_t; 161 164 162 165 /* Level 1 page tables access permissions */ … … 191 194 * @param pt Pointer to the page table to set. 192 195 */ 193 static inline void set_ptl0_addr(pte_ level0_t *pt)196 static inline void set_ptl0_addr(pte_t *pt) 194 197 { 195 198 asm volatile ( … … 205 208 * @param i Index of the entry to return. 206 209 */ 207 static inline int get_pt_level0_flags(pte_ level0_t *pt, size_t i)208 { 209 pte_level0_t *p = &pt[i] ;210 static inline int get_pt_level0_flags(pte_t *pt, size_t i) 211 { 212 pte_level0_t *p = &pt[i].l0; 210 213 int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); 211 214 … … 220 223 * @param i Index of the entry to return. 221 224 */ 222 static inline int get_pt_level1_flags(pte_ level1_t *pt, size_t i)223 { 224 pte_level1_t *p = &pt[i] ;225 static inline int get_pt_level1_flags(pte_t *pt, size_t i) 226 { 227 pte_level1_t *p = &pt[i].l1; 225 228 226 229 int dt = p->descriptor_type; … … 245 248 * @param flags new flags 246 249 */ 247 static inline void set_pt_level0_flags(pte_ level0_t *pt, size_t i, int flags)248 { 249 pte_level0_t *p = &pt[i] ;250 static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) 251 { 252 pte_level0_t *p = &pt[i].l0; 250 253 251 254 if (flags & PAGE_NOT_PRESENT) { … … 273 276 * @param flags New flags. 274 277 */ 275 static inline void set_pt_level1_flags(pte_ level1_t *pt, size_t i, int flags)276 { 277 pte_level1_t *p = &pt[i] ;278 static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) 279 { 280 pte_level1_t *p = &pt[i].l1; 278 281 279 282 if (flags & PAGE_NOT_PRESENT) { -
kernel/arch/arm32/include/types.h
r309ede1 r5f70118 87 87 #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ 88 88 89 /** Page table entry.90 *91 * We have different structs for level 0 and level 1 page table entries.92 * See page.h for definition of pte_level*_t.93 */94 typedef struct {95 unsigned dummy : 32;96 } pte_t;97 98 89 #endif 99 90 -
kernel/arch/arm32/src/arm32.c
r309ede1 r5f70118 48 48 #include <macros.h> 49 49 #include <string.h> 50 #include <arch/ras.h> 50 51 51 52 #ifdef MACHINE_testarm … … 88 89 exception_init(); 89 90 interrupt_init(); 91 92 /* Initialize Restartable Atomic Sequences support. */ 93 ras_init(); 90 94 91 95 machine_output_init(); … … 136 140 uint8_t *stck; 137 141 138 tlb_invalidate_all();139 142 stck = &THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]; 140 143 supervisor_sp = (uintptr_t) stck; -
kernel/arch/arm32/src/debug/stacktrace.c
r309ede1 r5f70118 1 1 /* 2 * Copyright (c) 20 05Jakub Jermar2 * Copyright (c) 2010 Jakub Jermar 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 /** @addtogroup mips3229 /** @addtogroup arm32 30 30 * @{ 31 31 */ … … 33 33 */ 34 34 35 #ifndef KERN_mips32_ARG_H_ 36 #define KERN_mips32_ARG_H_ 35 #include <stacktrace.h> 36 #include <syscall/copy.h> 37 #include <arch/types.h> 38 #include <typedefs.h> 37 39 38 #include <arch/types.h> 40 bool kernel_frame_pointer_validate(uintptr_t fp) 41 { 42 return false; 43 } 39 44 40 /** 41 * va_arg macro for MIPS32 - problem is that 64 bit values must be aligned on an 8-byte boundary (32bit values not) 42 * To satisfy this, paddings must be sometimes inserted. 43 */ 45 bool kernel_frame_pointer_prev(uintptr_t fp, uintptr_t *prev) 46 { 47 return false; 48 } 44 49 45 typedef uintptr_t va_list; 50 bool kernel_return_address_get(uintptr_t fp, uintptr_t *ra) 51 { 52 return false; 53 } 46 54 47 #define va_start(ap, lst) \ 48 ((ap) = (va_list)&(lst) + sizeof(lst)) 55 bool uspace_frame_pointer_validate(uintptr_t fp) 56 { 57 return false; 58 } 49 59 50 #define va_arg(ap, type) \ 51 (((type *)((ap) = (va_list)( (sizeof(type) <= 4) ? ((uintptr_t)((ap) + 2*4 - 1) & (~3)) : ((uintptr_t)((ap) + 2*8 -1) & (~7)) )))[-1]) 60 bool uspace_frame_pointer_prev(uintptr_t fp, uintptr_t *prev) 61 { 62 return false; 63 } 52 64 53 #define va_copy(dst,src) ((dst)=(src)) 54 55 #define va_end(ap) 56 57 #endif 65 bool uspace_return_address_get(uintptr_t fp, uintptr_t *ra) 66 { 67 return false; 68 } 58 69 59 70 /** @} -
kernel/arch/arm32/src/exc_handler.S
r309ede1 r5f70118 148 148 mov r0, #0 149 149 mov r1, r13 150 bl exc_dispatch150 bl ras_check 151 151 LOAD_REGS_FROM_STACK 152 152 … … 156 156 mov r0, #5 157 157 mov r1, r13 158 bl exc_dispatch158 bl ras_check 159 159 LOAD_REGS_FROM_STACK 160 160 … … 164 164 mov r0, #6 165 165 mov r1, r13 166 bl exc_dispatch166 bl ras_check 167 167 LOAD_REGS_FROM_STACK 168 168 … … 171 171 mov r0, #1 172 172 mov r1, r13 173 bl exc_dispatch173 bl ras_check 174 174 LOAD_REGS_FROM_STACK 175 175 … … 179 179 mov r0, #3 180 180 mov r1, r13 181 bl exc_dispatch181 bl ras_check 182 182 LOAD_REGS_FROM_STACK 183 183 … … 187 187 mov r0, #4 188 188 mov r1, r13 189 bl exc_dispatch189 bl ras_check 190 190 LOAD_REGS_FROM_STACK 191 191 … … 195 195 mov r0, #2 196 196 mov r1, r13 197 bl exc_dispatch197 bl ras_check 198 198 LOAD_REGS_FROM_STACK 199 199 -
kernel/arch/arm32/src/mm/as.c
r309ede1 r5f70118 36 36 #include <arch/mm/as.h> 37 37 #include <genarch/mm/as_pt.h> 38 #include <genarch/mm/page_pt.h> 38 39 #include <genarch/mm/asid_fifo.h> 39 40 #include <mm/as.h> 41 #include <mm/tlb.h> 40 42 #include <arch.h> 41 43 … … 49 51 } 50 52 53 void as_install_arch(as_t *as) 54 { 55 tlb_invalidate_all(); 56 } 57 51 58 /** @} 52 59 */ -
kernel/arch/arm32/src/mm/page.c
r309ede1 r5f70118 88 88 KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) { 89 89 panic("Unable to map physical memory %p (%d bytes).", 90 physaddr, size) 90 physaddr, size); 91 91 } 92 92 -
kernel/arch/arm32/src/userspace.c
r309ede1 r5f70118 35 35 36 36 #include <userspace.h> 37 #include <arch/ras.h> 37 38 38 39 /** Struct for holding all general purpose registers. … … 74 75 ustate.r1 = 0; 75 76 77 /* pass the RAS page address in %r2 */ 78 ustate.r2 = (uintptr_t) ras_page; 79 76 80 /* clear other registers */ 77 ustate.r 2 = ustate.r3 = ustate.r4 = ustate.r5=78 ustate.r 6 = ustate.r7 = ustate.r8 = ustate.r9 = ustate.r10 =79 ustate. r11 = ustate.r12 = ustate.lr = 0;81 ustate.r3 = ustate.r4 = ustate.r5 = ustate.r6 = ustate.r7 = 82 ustate.r8 = ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 83 ustate.lr = 0; 80 84 81 85 /* set user stack */ -
kernel/arch/ia32/Makefile.inc
r309ede1 r5f70118 34 34 BFD = binary 35 35 TARGET = i686-pc-linux-gnu 36 CLANG_ARCH = i386 36 37 TOOLCHAIN_DIR = $(CROSS_PREFIX)/ia32 37 38 … … 43 44 ICC_CFLAGS += $(CMN1) 44 45 SUNCC_CFLAGS += $(CMN1) 46 CLANG_CFLAGS += $(CMN1) 45 47 46 48 ## Accepted CPUs … … 71 73 GCC_CFLAGS += $(CMN2) 72 74 ICC_CFLAGS += $(CMN2) 75 CLANG_CFLAGS += $(CMN2) 73 76 74 77 ARCH_SOURCES = \ 75 78 arch/$(KARCH)/src/context.S \ 76 79 arch/$(KARCH)/src/debug/panic.s \ 80 arch/$(KARCH)/src/debug/stacktrace.c \ 81 arch/$(KARCH)/src/debug/stacktrace_asm.S \ 77 82 arch/$(KARCH)/src/delay.s \ 78 83 arch/$(KARCH)/src/asm.S \ -
kernel/arch/ia32/_link.ld.in
r309ede1 r5f70118 42 42 hardcoded_unmapped_kdata_size = .; 43 43 LONG(unmapped_kdata_end - unmapped_kdata_start); 44 . = ALIGN(8); 44 45 symbol_table = .; 45 46 *(symtab.*); /* Symbol table, must be LAST symbol! */ -
kernel/arch/ia32/include/context.h
r309ede1 r5f70118 49 49 #define SP_DELTA (8 + STACK_ITEM_SIZE) 50 50 51 #define context_set(c, _pc, stack, size) \ 52 do { \ 53 (c)->pc = (uintptr_t) (_pc); \ 54 (c)->sp = ((uintptr_t) (stack)) + (size) - SP_DELTA; \ 55 (c)->ebp = 0; \ 56 } while (0) 57 51 58 #endif /* KERNEL */ 52 59 -
kernel/arch/ia32/include/cpu.h
r309ede1 r5f70118 50 50 #include <arch/pm.h> 51 51 #include <arch/asm.h> 52 #include <arch/cpuid.h> 52 53 53 54 typedef struct { … … 56 57 unsigned int model; 57 58 unsigned int stepping; 59 cpuid_feature_info fi; 60 58 61 tss_t *tss; 59 62 -
kernel/arch/ia32/include/cpuid.h
r309ede1 r5f70118 63 63 64 64 struct __cpuid_feature_info { 65 unsigned : 23; 65 unsigned : 11; 66 unsigned sep : 1; 67 unsigned : 11; 66 68 unsigned mmx : 1; 67 69 unsigned fxsr : 1; -
kernel/arch/ia32/include/interrupt.h
r309ede1 r5f70118 69 69 #define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) 70 70 71 typedef struct {71 typedef struct istate { 72 72 uint32_t eax; 73 73 uint32_t ecx; 74 74 uint32_t edx; 75 uint32_t ebp; 75 76 76 77 uint32_t gs; … … 102 103 } 103 104 105 static inline unative_t istate_get_fp(istate_t *istate) 106 { 107 return istate->ebp; 108 } 109 104 110 extern void (* disable_irqs_function)(uint16_t irqmask); 105 111 extern void (* enable_irqs_function)(uint16_t irqmask); -
kernel/arch/ia32/include/mm/page.h
r309ede1 r5f70118 146 146 #define PFERR_CODE_RSVD (1 << 3) 147 147 148 static inline int get_pt_flags(pte_t *pt, size_t i) 148 /** Page Table Entry. */ 149 typedef struct { 150 unsigned present : 1; 151 unsigned writeable : 1; 152 unsigned uaccessible : 1; 153 unsigned page_write_through : 1; 154 unsigned page_cache_disable : 1; 155 unsigned accessed : 1; 156 unsigned dirty : 1; 157 unsigned pat : 1; 158 unsigned global : 1; 159 unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */ 160 unsigned avl : 2; 161 unsigned frame_address : 20; 162 } __attribute__ ((packed)) pte_t; 163 164 static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 149 165 { 150 166 pte_t *p = &pt[i]; -
kernel/arch/ia32/include/types.h
r309ede1 r5f70118 80 80 #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ 81 81 82 /** Page Table Entry. */83 typedef struct {84 unsigned present : 1;85 unsigned writeable : 1;86 unsigned uaccessible : 1;87 unsigned page_write_through : 1;88 unsigned page_cache_disable : 1;89 unsigned accessed : 1;90 unsigned dirty : 1;91 unsigned pat : 1;92 unsigned global : 1;93 unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */94 unsigned avl : 2;95 unsigned frame_address : 20;96 } __attribute__ ((packed)) pte_t;97 98 82 #endif 99 83 -
kernel/arch/ia32/src/asm.S
r309ede1 r5f70118 269 269 pushl %gs 270 270 271 pushl %ebp 271 272 pushl %edx 272 273 pushl %ecx … … 278 279 movw %ax, %es 279 280 280 cld 281 # stop stack traces here 282 xorl %ebp, %ebp 281 283 282 284 pushl %esp # *istate … … 290 292 popl %ecx 291 293 popl %edx 294 popl %ebp 292 295 293 296 popl %gs -
kernel/arch/ia32/src/boot/boot.S
r309ede1 r5f70118 85 85 pse_supported: 86 86 87 bt $(INTEL_SEP), %edx88 jc sep_supported89 90 movl $sep_msg, %esi91 jmp error_halt92 93 sep_supported:94 95 87 #include "vesa_prot.inc" 96 88 … … 102 94 pushl grub_eax 103 95 call arch_pre_main 96 97 # Create the first stack frame 98 pushl $0 99 movl %esp, %ebp 104 100 105 101 call main_bsp … … 225 221 .asciz "Page Size Extension not supported. System halted." 226 222 227 sep_msg:228 .asciz "SYSENTER/SYSEXIT not supported. System halted." -
kernel/arch/ia32/src/cpu/cpu.c
r309ede1 r5f70118 92 92 void cpu_arch_init(void) 93 93 { 94 cpuid_feature_info fi;95 94 cpuid_extended_feature_info efi; 96 95 cpu_info_t info; … … 102 101 CPU->fpu_owner = NULL; 103 102 104 cpuid( 1, &info);103 cpuid(INTEL_CPUID_STANDARD, &info); 105 104 106 fi.word = info.cpuid_edx;105 CPU->arch.fi.word = info.cpuid_edx; 107 106 efi.word = info.cpuid_ecx; 108 107 109 if ( fi.bits.fxsr)108 if (CPU->arch.fi.bits.fxsr) 110 109 fpu_fxsr(); 111 110 else 112 111 fpu_fsr(); 113 112 114 if ( fi.bits.sse) {113 if (CPU->arch.fi.bits.sse) { 115 114 asm volatile ( 116 115 "mov %%cr4, %[help]\n" … … 122 121 } 123 122 124 /* Setup fast SYSENTER/SYSEXIT syscalls */ 125 syscall_setup_cpu(); 123 if (CPU->arch.fi.bits.sep) { 124 /* Setup fast SYSENTER/SYSEXIT syscalls */ 125 syscall_setup_cpu(); 126 } 126 127 } 127 128 … … 132 133 CPU->arch.vendor = VendorUnknown; 133 134 if (has_cpuid()) { 134 cpuid( 0, &info);135 cpuid(INTEL_CPUID_LEVEL, &info); 135 136 136 137 /* … … 150 151 CPU->arch.vendor = VendorIntel; 151 152 152 cpuid( 1, &info);153 cpuid(INTEL_CPUID_STANDARD, &info); 153 154 CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f; 154 155 CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f; -
kernel/arch/ia32/src/debug/stacktrace.c
r309ede1 r5f70118 1 1 /* 2 * Copyright (c) 20 06 Josef Cejka2 * Copyright (c) 2010 Jakub Jermar 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 /** @addtogroup libcmips3229 /** @addtogroup ia32 30 30 * @{ 31 31 */ 32 32 /** @file 33 * @ingroup libcmips32eb34 33 */ 35 34 36 #ifndef LIBC_mips32_STACKARG_H_ 37 #define LIBC_mips32_STACKARG_H_ 35 #include <stacktrace.h> 36 #include <syscall/copy.h> 37 #include <arch/types.h> 38 #include <typedefs.h> 38 39 39 /* dont allow to define it second time in stdarg.h */ 40 #define __VARARGS_DEFINED40 #define FRAME_OFFSET_FP_PREV 0 41 #define FRAME_OFFSET_RA 1 41 42 42 #include <sys/types.h> 43 bool kernel_frame_pointer_validate(uintptr_t fp) 44 { 45 return fp != 0; 46 } 43 47 44 /** 45 * va_arg macro for MIPS32 - problem is that 64 bit values must be aligned on an 8-byte boundary (32bit values not) 46 * To satisfy this, paddings must be sometimes inserted. 47 */ 48 bool kernel_frame_pointer_prev(uintptr_t fp, uintptr_t *prev) 49 { 50 uint32_t *stack = (void *) fp; 51 *prev = stack[FRAME_OFFSET_FP_PREV]; 52 return true; 53 } 48 54 49 typedef uint8_t* va_list; 55 bool kernel_return_address_get(uintptr_t fp, uintptr_t *ra) 56 { 57 uint32_t *stack = (void *) fp; 58 *ra = stack[FRAME_OFFSET_RA]; 59 return true; 60 } 50 61 51 #define va_start(ap, lst) \ 52 ((ap) = (va_list)&(lst) + sizeof(lst)) 62 bool uspace_frame_pointer_validate(uintptr_t fp) 63 { 64 return fp != 0; 65 } 53 66 54 #define va_arg(ap, type) \ 55 (((type *)((ap) = (va_list)( (sizeof(type) <= 4) ? ((uint32_t)((ap) + 2*4 - 1) & (~3)) : ((uint32_t)((ap) + 2*8 -1) & (~7)) )))[-1]) 67 bool uspace_frame_pointer_prev(uintptr_t fp, uintptr_t *prev) 68 { 69 return !copy_from_uspace((void *) prev, 70 (uint32_t *) fp + FRAME_OFFSET_FP_PREV, sizeof(*prev)); 71 } 56 72 57 #define va_end(ap) 58 59 #endif 73 bool uspace_return_address_get(uintptr_t fp, uintptr_t *ra) 74 { 75 return !copy_from_uspace((void *) ra, (uint32_t *) fp + FRAME_OFFSET_RA, 76 sizeof(*ra)); 77 } 60 78 61 79 /** @} -
kernel/arch/ia32/src/ia32.c
r309ede1 r5f70118 68 68 #include <sysinfo/sysinfo.h> 69 69 #include <arch/boot/boot.h> 70 #include <memstr.h> 70 71 71 72 #ifdef CONFIG_SMP … … 169 170 i8042_wire(i8042_instance, kbrd); 170 171 trap_virtual_enable_irqs(1 << IRQ_KBD); 172 trap_virtual_enable_irqs(1 << IRQ_MOUSE); 171 173 } 172 174 } … … 176 178 * self-sufficient. 177 179 */ 178 sysinfo_set_item_val("kbd", NULL, true); 179 sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD); 180 sysinfo_set_item_val("kbd.address.physical", NULL, 180 sysinfo_set_item_val("i8042", NULL, true); 181 sysinfo_set_item_val("i8042.inr_a", NULL, IRQ_KBD); 182 sysinfo_set_item_val("i8042.inr_b", NULL, IRQ_MOUSE); 183 sysinfo_set_item_val("i8042.address.physical", NULL, 181 184 (uintptr_t) I8042_BASE); 182 sysinfo_set_item_val(" kbd.address.kernel", NULL,185 sysinfo_set_item_val("i8042.address.kernel", NULL, 183 186 (uintptr_t) I8042_BASE); 184 187 #endif -
kernel/arch/ia32/src/interrupt.c
r309ede1 r5f70118 53 53 #include <ddi/irq.h> 54 54 #include <symtab.h> 55 #include <stacktrace.h> 55 56 56 57 /* … … 79 80 printf("stack: %#lx, %#lx, %#lx, %#lx\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]); 80 81 printf(" %#lx, %#lx, %#lx, %#lx\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]); 82 83 stack_trace_istate(istate); 81 84 } 82 85 … … 96 99 decode_istate(istate); 97 100 panic("Unserviced interrupt: %d.", n); 101 } 102 103 static void de_fault(int n, istate_t *istate) 104 { 105 fault_if_from_uspace(istate, "Divide error."); 106 107 decode_istate(istate); 108 panic("Divide error."); 98 109 } 99 110 … … 215 226 } 216 227 228 exc_register(0, "de_fault", (iroutine) de_fault); 217 229 exc_register(7, "nm_fault", (iroutine) nm_fault); 218 230 exc_register(12, "ss_fault", (iroutine) ss_fault); -
kernel/arch/ia32/src/mm/page.c
r309ede1 r5f70118 80 80 { 81 81 if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) 82 panic("Unable to map physical memory %p (%d bytes).", physaddr, size) 82 panic("Unable to map physical memory %p (%d bytes).", physaddr, size); 83 83 84 84 uintptr_t virtaddr = PA2KA(last_frame); -
kernel/arch/ia32/src/proc/scheduler.c
r309ede1 r5f70118 61 61 SP_DELTA]; 62 62 63 /* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */ 64 write_msr(IA32_MSR_SYSENTER_ESP, kstk); 63 if (CPU->arch.fi.bits.sep) { 64 /* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */ 65 write_msr(IA32_MSR_SYSENTER_ESP, kstk); 66 } 65 67 66 68 /* Set kernel stack for CPL3 -> CPL0 switch via interrupt */ -
kernel/arch/ia32/src/smp/ap.S
r309ede1 r5f70118 78 78 addl $0x80000000, %esp # PA2KA(ctx.sp) 79 79 80 pushl $0 # create the first stack frame 81 movl %esp, %ebp 82 80 83 jmpl $KTEXT, $main_ap 81 84 -
kernel/arch/ia32/src/userspace.c
r309ede1 r5f70118 70 70 "movl %[uarg], %%eax\n" 71 71 72 /* %e bxis defined to hold pcb_ptr - set it to 0 */73 "xorl %%e bx, %%ebx\n"72 /* %edi is defined to hold pcb_ptr - set it to 0 */ 73 "xorl %%edi, %%edi\n" 74 74 75 75 "iret\n" -
kernel/arch/ia64/Makefile.inc
r309ede1 r5f70118 53 53 arch/$(KARCH)/src/context.S \ 54 54 arch/$(KARCH)/src/cpu/cpu.c \ 55 arch/$(KARCH)/src/debug/stacktrace.c \ 56 arch/$(KARCH)/src/debug/stacktrace_asm.S \ 55 57 arch/$(KARCH)/src/ivt.S \ 56 58 arch/$(KARCH)/src/interrupt.c \ -
kernel/arch/ia64/_link.ld.in
r309ede1 r5f70118 7 7 */ 8 8 9 #define LOAD_ADDRESS_V 0xe000000004404000 10 #define LOAD_ADDRESS_P 0x0000000004404000 11 9 12 ENTRY(kernel_image_start) 10 13 11 14 SECTIONS { 12 .image 0xe000000004404000: AT (0x0000000004404000) {15 .image LOAD_ADDRESS_V: AT (LOAD_ADDRESS_P) { 13 16 ktext_start = .; 14 17 *(K_TEXT_START); … … 21 24 *(.opd) 22 25 *(.data .data.*) 26 hardcoded_load_address = .; 27 QUAD(LOAD_ADDRESS_V); 28 hardcoded_ktext_size = .; 29 QUAD(ktext_end - ktext_start); 30 hardcoded_kdata_size = .; 31 QUAD(kdata_end - kdata_start); 23 32 *(.got .got.*) 24 33 *(.sdata) … … 28 37 *(COMMON); 29 38 39 . = ALIGN(8); 30 40 symbol_table = .; 31 41 *(symtab.*); /* Symbol table, must be LAST symbol!*/ … … 38 48 } 39 49 40 _hardcoded_ktext_size = ktext_end - ktext_start;41 _hardcoded_kdata_size = kdata_end - kdata_start;42 _hardcoded_load_address = 0xe000000004404000;43 44 50 } -
kernel/arch/ia64/include/asm.h
r309ede1 r5f70118 422 422 asm volatile ( 423 423 "rsm %[mask]\n" 424 ";;\n" 425 "srlz.d\n" 424 426 :: [mask] "i" (PSR_PK_MASK) 425 427 ); -
kernel/arch/ia64/include/interrupt.h
r309ede1 r5f70118 72 72 #define EOI 0 /**< The actual value doesn't matter. */ 73 73 74 typedef struct {74 typedef struct istate { 75 75 uint128_t f2; 76 76 uint128_t f3; … … 143 143 } 144 144 145 static inline unative_t istate_get_fp(istate_t *istate) 146 { 147 return 0; /* FIXME */ 148 } 149 145 150 static inline int istate_from_uspace(istate_t *istate) 146 151 { -
kernel/arch/ia64/src/cpu/cpu.c
r309ede1 r5f70118 37 37 #include <arch/register.h> 38 38 #include <print.h> 39 #include <memstr.h> 39 40 40 41 void cpu_arch_init(void) -
kernel/arch/ia64/src/debug/stacktrace.c
r309ede1 r5f70118 1 1 /* 2 * Copyright (c) 20 05Jakub Jermar2 * Copyright (c) 2010 Jakub Jermar 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 /** @addtogroup generic29 /** @addtogroup ia64 30 30 * @{ 31 31 */ … … 33 33 */ 34 34 35 /* 36 * Variable argument list manipulation macros 37 * for architectures using stack to pass arguments. 38 */ 39 40 #ifndef KERN_STACKARG_H_ 41 #define KERN_STACKARG_H_ 35 #include <stacktrace.h> 36 #include <syscall/copy.h> 37 #include <arch/types.h> 38 #include <typedefs.h> 42 39 43 #include <arch/types.h> 40 bool kernel_frame_pointer_validate(uintptr_t fp) 41 { 42 return false; 43 } 44 44 45 typedef struct va_list { 46 int pos; 47 uint8_t *last;48 } va_list;45 bool kernel_frame_pointer_prev(uintptr_t fp, uintptr_t *prev) 46 { 47 return false; 48 } 49 49 50 #define va_start(ap, lst) \ 51 (ap).pos = sizeof(lst); \ 52 (ap).last = (uint8_t *) &(lst) 50 bool kernel_return_address_get(uintptr_t fp, uintptr_t *ra) 51 { 52 return false; 53 } 53 54 54 #define va_arg(ap, type) \ 55 (*((type *)((ap).last + ((ap).pos += sizeof(type)) - sizeof(type)))) 55 bool uspace_frame_pointer_validate(uintptr_t fp) 56 { 57 return false; 58 } 56 59 57 #define va_copy(dst, src) dst = src 58 #define va_end(ap) 60 bool uspace_frame_pointer_prev(uintptr_t fp, uintptr_t *prev) 61 { 62 return false; 63 } 59 64 60 61 #endif 65 bool uspace_return_address_get(uintptr_t fp, uintptr_t *ra) 66 { 67 return false; 68 } 62 69 63 70 /** @} -
kernel/arch/ia64/src/ivt.S
r309ede1 r5f70118 391 391 392 392 /* 10. call handler */ 393 movl r1 = _hardcoded_load_address393 movl r1 = kernel_image_start 394 394 395 395 mov b1 = loc2 -
kernel/arch/ia64/src/mm/as.c
r309ede1 r5f70118 73 73 rr.map.ps = PAGE_WIDTH; 74 74 rr_write(i, rr.word); 75 srlz_d(); 76 srlz_i(); 75 77 } 76 srlz_d();77 srlz_i();78 78 } 79 79 -
kernel/arch/ia64/src/start.S
r309ede1 r5f70118 186 186 movl r20 = (VRN_KERNEL << VRN_SHIFT) ;; 187 187 or r20 = r20, r1 ;; 188 movl r1 = _hardcoded_load_address188 movl r1 = kernel_image_start 189 189 190 190 /* 191 * Initialize hardcoded_* variables. Do only BSP191 * Initialize bootinfo on BSP. 192 192 */ 193 (p3) movl r14 = _hardcoded_ktext_size 194 (p3) movl r15 = _hardcoded_kdata_size 195 (p3) movl r16 = _hardcoded_load_address ;; 196 (p3) addl r17 = @gprel(hardcoded_ktext_size), gp 197 (p3) addl r18 = @gprel(hardcoded_kdata_size), gp 198 (p3) addl r19 = @gprel(hardcoded_load_address), gp 199 (p3) addl r21 = @gprel(bootinfo), gp 200 ;; 201 (p3) st8 [r17] = r14 202 (p3) st8 [r18] = r15 203 (p3) st8 [r19] = r16 193 (p3) addl r21 = @gprel(bootinfo), gp ;; 204 194 (p3) st8 [r21] = r20 205 195 -
kernel/arch/mips32/Makefile.inc
r309ede1 r5f70118 70 70 arch/$(KARCH)/src/debugger.c \ 71 71 arch/$(KARCH)/src/cpu/cpu.c \ 72 arch/$(KARCH)/src/debug/stacktrace.c \ 73 arch/$(KARCH)/src/debug/stacktrace_asm.S \ 72 74 arch/$(KARCH)/src/mm/frame.c \ 73 75 arch/$(KARCH)/src/mm/page.c \ -
kernel/arch/mips32/_link.ld.in
r309ede1 r5f70118 38 38 *(.bss); /* uninitialized static variables */ 39 39 *(COMMON); /* global variables */ 40 . = ALIGN(8); 40 41 symbol_table = .; 41 42 *(symtab.*); -
kernel/arch/mips32/include/exception.h
r309ede1 r5f70118 58 58 #define EXC_VCED 31 59 59 60 typedef struct {60 typedef struct istate { 61 61 uint32_t at; 62 62 uint32_t v0; … … 102 102 return istate->epc; 103 103 } 104 static inline unative_t istate_get_fp(istate_t *istate) 105 { 106 return 0; /* FIXME */ 107 } 104 108 105 109 extern void exception(istate_t *istate); -
kernel/arch/mips32/include/mm/page.h
r309ede1 r5f70118 141 141 #include <arch/exception.h> 142 142 143 static inline int get_pt_flags(pte_t *pt, size_t i) 143 /** Page Table Entry. */ 144 typedef struct { 145 unsigned g : 1; /**< Global bit. */ 146 unsigned p : 1; /**< Present bit. */ 147 unsigned d : 1; /**< Dirty bit. */ 148 unsigned cacheable : 1; /**< Cacheable bit. */ 149 unsigned : 1; /**< Unused. */ 150 unsigned soft_valid : 1; /**< Valid content even if not present. */ 151 unsigned pfn : 24; /**< Physical frame number. */ 152 unsigned w : 1; /**< Page writable bit. */ 153 unsigned a : 1; /**< Accessed bit. */ 154 } pte_t; 155 156 157 static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 144 158 { 145 159 pte_t *p = &pt[i]; -
kernel/arch/mips32/include/types.h
r309ede1 r5f70118 80 80 #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ 81 81 82 /** Page Table Entry. */83 typedef struct {84 unsigned g : 1; /**< Global bit. */85 unsigned p : 1; /**< Present bit. */86 unsigned d : 1; /**< Dirty bit. */87 unsigned cacheable : 1; /**< Cacheable bit. */88 unsigned : 1; /**< Unused. */89 unsigned soft_valid : 1; /**< Valid content even if not present. */90 unsigned pfn : 24; /**< Physical frame number. */91 unsigned w : 1; /**< Page writable bit. */92 unsigned a : 1; /**< Accessed bit. */93 } pte_t;94 95 82 #endif 96 83 -
kernel/arch/mips32/src/debug/stacktrace.c
r309ede1 r5f70118 1 1 /* 2 * Copyright (c) 20 05Jakub Jermar2 * Copyright (c) 2010 Jakub Jermar 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 /** @addtogroup libcia3229 /** @addtogroup mips32 30 30 * @{ 31 31 */ … … 33 33 */ 34 34 35 /* 36 * Variable argument list manipulation macros 37 * for architectures using stack to pass arguments. 38 */ 39 40 #ifndef LIBC_ia32_STACKARG_H_ 41 #define LIBC_ia32_STACKARG_H_ 35 #include <stacktrace.h> 36 #include <syscall/copy.h> 37 #include <arch/types.h> 38 #include <typedefs.h> 42 39 43 #include <sys/types.h> 40 bool kernel_frame_pointer_validate(uintptr_t fp) 41 { 42 return false; 43 } 44 44 45 /* dont allow to define it second time in stdarg.h */ 46 #define __VARARGS_DEFINED 45 bool kernel_frame_pointer_prev(uintptr_t fp, uintptr_t *prev) 46 { 47 return false; 48 } 47 49 48 typedef struct va_list { 49 int pos; 50 uint8_t *last;51 } va_list;50 bool kernel_return_address_get(uintptr_t fp, uintptr_t *ra) 51 { 52 return false; 53 } 52 54 53 #define va_start(ap, lst) \ 54 (ap).pos = sizeof(lst); \ 55 (ap).last = (uint8_t *) &(lst) 55 bool uspace_frame_pointer_validate(uintptr_t fp) 56 { 57 return false; 58 } 56 59 57 #define va_arg(ap, type) \ 58 (*((type *)((ap).last + ((ap).pos += sizeof(type) ) - sizeof(type)))) 60 bool uspace_frame_pointer_prev(uintptr_t fp, uintptr_t *prev) 61 { 62 return false; 63 } 59 64 60 #define va_end(ap)61 62 63 #endif 65 bool uspace_return_address_get(uintptr_t fp, uintptr_t *ra) 66 { 67 return false; 68 } 64 69 65 70 /** @} -
kernel/arch/ppc32/Makefile.inc
r309ede1 r5f70118 46 46 arch/$(KARCH)/src/context.S \ 47 47 arch/$(KARCH)/src/debug/panic.s \ 48 arch/$(KARCH)/src/debug/stacktrace.c \ 49 arch/$(KARCH)/src/debug/stacktrace_asm.S \ 48 50 arch/$(KARCH)/src/fpu_context.S \ 49 51 arch/$(KARCH)/src/boot/boot.S \ -
kernel/arch/ppc32/_link.ld.in
r309ede1 r5f70118 51 51 *(COMMON); /* global variables */ 52 52 53 . = ALIGN(8); 53 54 symbol_table = .; 54 55 *(symtab.*); /* Symbol table, must be LAST symbol!*/ -
kernel/arch/ppc32/include/exception.h
r309ede1 r5f70118 39 39 #include <arch/regutils.h> 40 40 41 typedef struct {41 typedef struct istate { 42 42 uint32_t r0; 43 43 uint32_t r2; … … 98 98 } 99 99 100 static inline unative_t istate_get_fp(istate_t *istate) 101 { 102 return istate->sp; 103 } 104 100 105 #endif 101 106 -
kernel/arch/ppc32/include/mm/page.h
r309ede1 r5f70118 131 131 #include <arch/interrupt.h> 132 132 133 static inline int get_pt_flags(pte_t *pt, size_t i) 133 /** Page Table Entry. */ 134 typedef struct { 135 unsigned present : 1; /**< Present bit. */ 136 unsigned page_write_through : 1; /**< Write thought caching. */ 137 unsigned page_cache_disable : 1; /**< No caching. */ 138 unsigned accessed : 1; /**< Accessed bit. */ 139 unsigned global : 1; /**< Global bit. */ 140 unsigned valid : 1; /**< Valid content even if not present. */ 141 unsigned pfn : 20; /**< Physical frame number. */ 142 } pte_t; 143 144 static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 134 145 { 135 146 pte_t *p = &pt[i]; -
kernel/arch/ppc32/include/types.h
r309ede1 r5f70118 82 82 #define PRIxn "x" 83 83 84 /** Page Table Entry. */85 typedef struct {86 unsigned present : 1; /**< Present bit. */87 unsigned page_write_through : 1; /**< Write thought caching. */88 unsigned page_cache_disable : 1; /**< No caching. */89 unsigned accessed : 1; /**< Accessed bit. */90 unsigned global : 1; /**< Global bit. */91 unsigned valid : 1; /**< Valid content even if not present. */92 unsigned pfn : 20; /**< Physical frame number. */93 } pte_t;94 95 84 #endif 96 85 -
kernel/arch/ppc32/src/mm/as.c
r309ede1 r5f70118 35 35 #include <arch/mm/as.h> 36 36 #include <genarch/mm/as_pt.h> 37 #include <genarch/mm/page_pt.h> 37 38 #include <genarch/mm/asid_fifo.h> 38 39 #include <arch.h> -
kernel/arch/ppc32/src/mm/page.c
r309ede1 r5f70118 51 51 KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) 52 52 panic("Unable to map physical memory %p (%" PRIs " bytes).", 53 physaddr, size) 53 physaddr, size); 54 54 55 55 uintptr_t virtaddr = PA2KA(last_frame); -
kernel/arch/ppc32/src/mm/tlb.c
r309ede1 r5f70118 38 38 #include <interrupt.h> 39 39 #include <mm/as.h> 40 #include <mm/page.h> 40 41 #include <arch.h> 41 42 #include <print.h> -
kernel/arch/ppc32/src/ppc32.c
r309ede1 r5f70118 44 44 #include <genarch/ofw/pci.h> 45 45 #include <userspace.h> 46 #include <mm/page.h> 46 47 #include <proc/uarg.h> 47 48 #include <console/console.h> -
kernel/arch/sparc64/Makefile.inc
r309ede1 r5f70118 54 54 ARCH_SOURCES = \ 55 55 arch/$(KARCH)/src/cpu/cpu.c \ 56 arch/$(KARCH)/src/debug/stacktrace.c \ 57 arch/$(KARCH)/src/debug/stacktrace_asm.S \ 56 58 arch/$(KARCH)/src/asm.S \ 57 59 arch/$(KARCH)/src/panic.S \ -
kernel/arch/sparc64/_link.ld.in
r309ede1 r5f70118 36 36 *(COMMON); /* global variables */ 37 37 38 . = ALIGN(8); 38 39 symbol_table = .; 39 40 *(symtab.*); /* Symbol table, must be LAST symbol!*/ -
kernel/arch/sparc64/include/interrupt.h
r309ede1 r5f70118 50 50 }; 51 51 52 typedef struct {52 typedef struct istate { 53 53 uint64_t tnpc; 54 54 uint64_t tpc; … … 71 71 } 72 72 73 static inline unative_t istate_get_fp(istate_t *istate) 74 { 75 return 0; /* TODO */ 76 } 77 73 78 #endif 74 79 -
kernel/arch/sparc64/src/context.S
r309ede1 r5f70118 28 28 29 29 #include <arch/context_offset.h> 30 31 /** 32 * Both context_save_arch() and context_restore_arch() are 33 * leaf-optimized procedures. This kind of optimization 34 * is very important and prevents any implicit window 35 * spill/fill/clean traps in these very core kernel 36 * functions. 37 */ 38 39 #include <arch/context_offset.h> 30 #include <arch/arch.h> 31 #include <arch/regdef.h> 40 32 41 33 .text … … 44 36 .global context_restore_arch 45 37 38 /* 39 * context_save_arch() is required not to create its own stack frame. See the 40 * generic context.h for explanation. 41 */ 46 42 context_save_arch: 43 # 44 # Force all our active register windows to memory so that we can find 45 # them there even if e.g. the thread is migrated to another processor. 46 # 47 flushw 48 47 49 CONTEXT_SAVE_ARCH_CORE %o0 48 50 retl … … 51 53 context_restore_arch: 52 54 # 53 # Flush all active windows. 54 # This is essential, because CONTEXT_LOAD overwrites 55 # %sp of CWP - 1 with the value written to %fp of CWP. 56 # Flushing all active windows mitigates this problem 57 # as CWP - 1 becomes the overlap window. 55 # Forget all previous windows, they are not going to be needed again. 56 # Enforce a window fill on the next RESTORE instruction by setting 57 # CANRESTORE to zero and other window configuration registers 58 # accordingly. Note that the same can be achieved by executing the 59 # FLUSHW instruction, but since we don't need to remember the previous 60 # windows, we do the former and save thus some unnecessary window 61 # spills. 58 62 # 59 flushw 60 63 rdpr %pstate, %l0 64 andn %l0, PSTATE_IE_BIT, %l1 65 wrpr %l1, %pstate 66 wrpr %g0, 0, %canrestore 67 wrpr %g0, 0, %otherwin 68 wrpr %g0, NWINDOWS - 2, %cansave 69 wrpr %l0, %pstate 70 61 71 CONTEXT_RESTORE_ARCH_CORE %o0 62 72 retl -
kernel/arch/sparc64/src/mm/tlb.c
r309ede1 r5f70118 37 37 #include <mm/as.h> 38 38 #include <mm/asid.h> 39 #include <genarch/mm/page_ht.h> 39 40 #include <arch/mm/frame.h> 40 41 #include <arch/mm/page.h> -
kernel/arch/sparc64/src/trap/trap_table.S
r309ede1 r5f70118 652 652 * spilled to kernel memory (i.e. register window buffer). Moreover, 653 653 * if the scheduler was called in the meantime, all valid windows 654 * belonging to other threads were spilled by context_ restore().654 * belonging to other threads were spilled by context_save(). 655 655 * If OTHERWIN is non-zero, then some userspace windows are still 656 656 * valid. Others might have been spilled. However, the CWP pointer
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