Changeset 3396f59 in mainline for arch/amd64/src/cpu/cpu.c

Timestamp:

2005-09-04T08:28:55Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8ff2f3f

Parents:

005384ad

Message:

Fixed gdtr naming issues after ia32 changes.
Fixed stack alignment on new thread to by multiple of 16,
we are now ABI-correct and we do not #GP on va_arg to boot.
Fixed bad exception register names reporting.
Fixed bad _hardcoded_load_addr, which caused allocation of kernel text
frames.

File:

• arch/amd64/src/cpu/cpu.c (modified) (2 diffs)

arch/amd64/src/cpu/cpu.c

@@ -61 +61 @@
 };
 
+
+/** Setup flags on processor so that we can use the FPU
+ *
+ * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
+ * cr0.em = 0 -> we do not emulate coprocessor
+ * cr0.mp = 1 -> we do want lazy context switch
+ */
+void cpu_setup_fpu(void)
+{
+        __asm__ volatile (
+                "movq %%cr0, %%rax;"
+                "btsq $1, %%rax;" /* cr0.mp */
+                "btrq $2, %%rax;"  /* cr0.em */
+                "movq %%rax, %%cr0;"
+
+                "movq %%cr4, %%rax;"
+                "bts $9, %%rax;" /* cr4.osfxsr */
+                "movq %%rax, %%cr4;"
+                :
+                :
+                :"%rax"
+                );
+}
+
+/** Set the TS flag to 1. 
+ *
+ * If a thread accesses coprocessor, exception is run, which 
+ * does a lazy fpu context switch.
+ *
+ */
 void set_TS_flag(void)
 {
         __asm__ volatile (
                 "mov %%cr0,%%rax;"
-                "or $8,%%rax;"
+                "bts $3,%%rax;"
                 "mov %%rax,%%cr0;"
                 :
@@ -77 +107 @@
         __asm__ volatile (
                 "mov %%cr0,%%rax;"
-                "btc $4,%%rax;"
+                "btr $3,%%rax;"
                 "mov %%rax,%%cr0;"
                 :