source: mainline/arch/amd64/src/cpu/cpu.c@ 3396f59

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3396f59 was 3396f59, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Fixed gdtr naming issues after ia32 changes.
Fixed stack alignment on new thread to by multiple of 16,
we are now ABI-correct and we do not #GP on va_arg to boot.
Fixed bad exception register names reporting.
Fixed bad _hardcoded_load_addr, which caused allocation of kernel text
frames.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/cpu.h>
30#include <arch/cpuid.h>
31#include <arch/pm.h>
32
33#include <arch.h>
34#include <arch/types.h>
35#include <print.h>
36#include <typedefs.h>
37
38/*
39 * Identification of CPUs.
40 * Contains only non-MP-Specification specific SMP code.
41 */
42#define AMD_CPUID_EBX 0x68747541
43#define AMD_CPUID_ECX 0x444d4163
44#define AMD_CPUID_EDX 0x69746e65
45
46#define INTEL_CPUID_EBX 0x756e6547
47#define INTEL_CPUID_ECX 0x6c65746e
48#define INTEL_CPUID_EDX 0x49656e69
49
50
51enum vendor {
52 VendorUnknown=0,
53 VendorAMD,
54 VendorIntel
55};
56
57static char *vendor_str[] = {
58 "Unknown Vendor",
59 "AuthenticAMD",
60 "GenuineIntel"
61};
62
63
64/** Setup flags on processor so that we can use the FPU
65 *
66 * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
67 * cr0.em = 0 -> we do not emulate coprocessor
68 * cr0.mp = 1 -> we do want lazy context switch
69 */
70void cpu_setup_fpu(void)
71{
72 __asm__ volatile (
73 "movq %%cr0, %%rax;"
74 "btsq $1, %%rax;" /* cr0.mp */
75 "btrq $2, %%rax;" /* cr0.em */
76 "movq %%rax, %%cr0;"
77
78 "movq %%cr4, %%rax;"
79 "bts $9, %%rax;" /* cr4.osfxsr */
80 "movq %%rax, %%cr4;"
81 :
82 :
83 :"%rax"
84 );
85}
86
87/** Set the TS flag to 1.
88 *
89 * If a thread accesses coprocessor, exception is run, which
90 * does a lazy fpu context switch.
91 *
92 */
93void set_TS_flag(void)
94{
95 __asm__ volatile (
96 "mov %%cr0,%%rax;"
97 "bts $3,%%rax;"
98 "mov %%rax,%%cr0;"
99 :
100 :
101 :"%rax"
102 );
103}
104
105void reset_TS_flag(void)
106{
107 __asm__ volatile (
108 "mov %%cr0,%%rax;"
109 "btr $3,%%rax;"
110 "mov %%rax,%%cr0;"
111 :
112 :
113 :"%rax"
114 );
115}
116
117void cpu_arch_init(void)
118{
119 CPU->arch.tss = tss_p;
120 CPU->fpu_owner=NULL;
121}
122
123
124void cpu_identify(void)
125{
126 cpu_info_t info;
127 int i;
128
129 CPU->arch.vendor = VendorUnknown;
130 if (has_cpuid()) {
131 cpuid(0, &info);
132
133 /*
134 * Check for AMD processor.
135 */
136 if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
137 CPU->arch.vendor = VendorAMD;
138 }
139
140 /*
141 * Check for Intel processor.
142 */
143 if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
144 CPU->arch.vendor = VendorIntel;
145 }
146
147 cpuid(1, &info);
148 CPU->arch.family = (info.cpuid_eax>>8)&0xf;
149 CPU->arch.model = (info.cpuid_eax>>4)&0xf;
150 CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
151 }
152}
153
154void cpu_print_report(cpu_t* m)
155{
156 printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
157 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
158 m->frequency_mhz);
159}
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