source: mainline/arch/amd64/src/cpu/cpu.c@ e515167d

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e515167d was e515167d, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Added basic FPU context (not working).
Added CPU utilities from ia32
Fixed bug in vm.c that wanted PTL to be mapped in bottom memory.

  • Property mode set to 100644
File size: 3.2 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/cpu.h>
30#include <arch/cpuid.h>
31#include <arch/pm.h>
32
33#include <arch.h>
34#include <arch/types.h>
35#include <print.h>
36#include <typedefs.h>
37
38/*
39 * Identification of CPUs.
40 * Contains only non-MP-Specification specific SMP code.
41 */
42#define AMD_CPUID_EBX 0x68747541
43#define AMD_CPUID_ECX 0x444d4163
44#define AMD_CPUID_EDX 0x69746e65
45
46#define INTEL_CPUID_EBX 0x756e6547
47#define INTEL_CPUID_ECX 0x6c65746e
48#define INTEL_CPUID_EDX 0x49656e69
49
50
51enum vendor {
52 VendorUnknown=0,
53 VendorAMD,
54 VendorIntel
55};
56
57static char *vendor_str[] = {
58 "Unknown Vendor",
59 "AuthenticAMD",
60 "GenuineIntel"
61};
62
63void set_TS_flag(void)
64{
65 __asm__ volatile (
66 "mov %%cr0,%%rax;"
67 "or $8,%%rax;"
68 "mov %%rax,%%cr0;"
69 :
70 :
71 :"%rax"
72 );
73}
74
75void reset_TS_flag(void)
76{
77 __asm__ volatile (
78 "mov %%cr0,%%rax;"
79 "btc $4,%%rax;"
80 "mov %%rax,%%cr0;"
81 :
82 :
83 :"%rax"
84 );
85}
86
87void cpu_arch_init(void)
88{
89 CPU->arch.tss = tss_p;
90 CPU->fpu_owner=NULL;
91}
92
93
94void cpu_identify(void)
95{
96 cpu_info_t info;
97 int i;
98
99 CPU->arch.vendor = VendorUnknown;
100 if (has_cpuid()) {
101 cpuid(0, &info);
102
103 /*
104 * Check for AMD processor.
105 */
106 if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
107 CPU->arch.vendor = VendorAMD;
108 }
109
110 /*
111 * Check for Intel processor.
112 */
113 if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
114 CPU->arch.vendor = VendorIntel;
115 }
116
117 cpuid(1, &info);
118 CPU->arch.family = (info.cpuid_eax>>8)&0xf;
119 CPU->arch.model = (info.cpuid_eax>>4)&0xf;
120 CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
121 }
122}
123
124void cpu_print_report(cpu_t* m)
125{
126 printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
127 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
128 m->frequency_mhz);
129}
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