Changeset 22f7769 in mainline for arch/mips32/src

Timestamp:

2005-10-17T23:31:41Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4b2c872d

Parents:

75eacab

Message:

Rename cpu_priority_{high|low|restore|read} functions to interrupts_{disable|enable|restore|read}.
Rename pri_t to ipl_t (Interrupt Priority Level).
Rename thread_t::pri to thread_t::priority.

Location:

arch/mips32/src

Files:

• drivers/arc.c (modified) (1 diff)
• exception.c (modified) (1 diff)
• interrupt.c (modified) (1 diff)
• mips32.c (modified) (1 diff)
• mm/asid.c (modified) (7 diffs)
• mm/tlb.c (modified) (2 diffs)
• mm/vm.c (modified) (1 diff)

arch/mips32/src/drivers/arc.c

@@ -176 +176 @@
 {
         __u32 cnt;
-        pri_t pri;
+        ipl_t ipl;
 
         /* TODO: Should be spinlock? */
-        pri = cpu_priority_high();
+        ipl = interrupts_disable();
         arc_entry->write(1, &ch, 1, &cnt);
-        cpu_priority_restore(pri);
+        interrupts_restore(ipl);
         
 }

arch/mips32/src/exception.c

@@ -47 +47 @@
          * NOTE ON OPERATION ORDERING
          *
-         * On entry, cpu_priority_high() must be called before 
+         * On entry, interrupts_disable() must be called before 
          * exception bit is cleared.
          */
 
-        cpu_priority_high();
+        interrupts_disable();
         cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
                                                 cp0_status_um_bit));

arch/mips32/src/interrupt.c

@@ -53 +53 @@
 }
 
-pri_t cpu_priority_high(void)
+/** Disable interrupts.
+ *
+ * @return Old interrupt priority level.
+ */
+ipl_t interrupts_disable(void)
 {
-        pri_t pri = (pri_t) cp0_status_read();
-        cp0_status_write(pri & ~cp0_status_ie_enabled_bit);
-        return pri;
+        ipl_t ipl = (ipl_t) cp0_status_read();
+        cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
+        return ipl;
 }
 
-pri_t cpu_priority_low(void)
+/** Enable interrupts.
+ *
+ * @return Old interrupt priority level.
+ */
+ipl_t interrupts_enable(void)
 {
-        pri_t pri = (pri_t) cp0_status_read();
-        cp0_status_write(pri | cp0_status_ie_enabled_bit);
-        return pri;
+        ipl_t ipl = (ipl_t) cp0_status_read();
+        cp0_status_write(ipl | cp0_status_ie_enabled_bit);
+        return ipl;
 }
 
-void cpu_priority_restore(pri_t pri)
+/** Restore interrupt priority level.
+ *
+ * @param ipl Saved interrupt priority level.
+ */
+void interrupts_restore(ipl_t ipl)
 {
-        cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit));
+        cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
 }
 
-pri_t cpu_priority_read(void)
+/** Read interrupt priority level.
+ *
+ * @return Current interrupt priority level.
+ */
+ipl_t interrupts_read(void)
 {
         return cp0_status_read();

arch/mips32/src/mips32.c

@@ -53 +53 @@
 {
         /* It is not assumed by default */
-        cpu_priority_high();
+        interrupts_disable();
 
         init_arc();

arch/mips32/src/mm/asid.c

@@ -45 +45 @@
 asid_t asid_get(void)
 {
-        pri_t pri;
+        ipl_t ipl;
         int i, j;
         count_t min;
@@ -51 +51 @@
         min = (unsigned) -1;
         
-        pri = cpu_priority_high();
+        ipl = interrupts_disable();
         spinlock_lock(&asid_usage_lock);
         
@@ -66 +66 @@
 
         spinlock_unlock(&asid_usage_lock);
-        cpu_priority_restore(pri);
+        interrupts_restore(ipl);
 
         return i;
@@ -79 +79 @@
 void asid_put(asid_t asid)
 {
-        pri_t pri;
+        ipl_t ipl;
 
-        pri = cpu_priority_high();
+        ipl = interrupts_disable();
         spinlock_lock(&asid_usage_lock);
 
@@ -90 +90 @@
 
         spinlock_unlock(&asid_usage_lock);
-        cpu_priority_restore(pri);
+        interrupts_restore(ipl);
 }
 
@@ -104 +104 @@
 {
         bool has_conflicts = false;
-        pri_t pri;
+        ipl_t ipl;
 
         ASSERT(asid != ASID_INVALID);
 
-        pri = cpu_priority_high();
+        ipl = interrupts_disable();
         spinlock_lock(&asid_usage_lock);
 
@@ -115 +115 @@
 
         spinlock_unlock(&asid_usage_lock);
-        cpu_priority_restore(pri);
+        interrupts_restore(ipl);
 
         return has_conflicts;

arch/mips32/src/mm/tlb.c

@@ -316 +316 @@
 {
         entry_hi_t hi;
-        pri_t pri;
+        ipl_t ipl;
         int i;  
         
         ASSERT(asid != ASID_INVALID);
 
-        pri = cpu_priority_high();
+        ipl = interrupts_disable();
         
         for (i = 0; i < TLB_SIZE; i++) {
@@ -337 +337 @@
         }
         
-        cpu_priority_restore(pri);
+        interrupts_restore(ipl);
 }
 

arch/mips32/src/mm/vm.c

@@ -42 +42 @@
 {
         entry_hi_t hi;
-        pri_t pri;
+        ipl_t ipl;
         
         hi.value = cp0_entry_hi_read();
 
-        pri = cpu_priority_high();
+        ipl = interrupts_disable();
         spinlock_lock(&vm->lock);
         hi.asid = vm->asid;
         cp0_entry_hi_write(hi.value);   
         spinlock_lock(&vm->unlock);
-        cpu_priority_restore(pri);
+        interrupts_restore(ipl);
 }