| 1 | /*
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| 2 | * Copyright (c) 2017 Petr Manek
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup drvusbxhci
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief The host controller endpoint management.
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| 34 | */
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| 35 |
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| 36 | #include <usb/host/endpoint.h>
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| 37 | #include <usb/descriptor.h>
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| 38 |
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| 39 | #include <errno.h>
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| 40 | #include <macros.h>
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| 41 |
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| 42 | #include "hc.h"
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| 43 | #include "bus.h"
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| 44 | #include "commands.h"
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| 45 | #include "endpoint.h"
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| 46 |
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| 47 | /** Initialize new XHCI endpoint.
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| 48 | * @param[in] xhci_ep Allocated XHCI endpoint to initialize.
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| 49 | * @param[in] dev Device, to which the endpoint belongs.
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| 50 | * @param[in] desc USB endpoint descriptor carrying configuration data.
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| 51 | *
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| 52 | * @return Error code.
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| 53 | */
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| 54 | int xhci_endpoint_init(xhci_endpoint_t *xhci_ep, device_t *dev, const usb_endpoint_desc_t *desc)
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| 55 | {
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| 56 | assert(xhci_ep);
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| 57 |
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| 58 | endpoint_t *ep = &xhci_ep->base;
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| 59 |
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| 60 | endpoint_init(ep, dev, desc);
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| 61 |
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| 62 | xhci_ep->max_streams = desc->usb3.max_streams;
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| 63 | xhci_ep->max_burst = desc->usb3.max_burst;
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| 64 | xhci_ep->mult = desc->usb3.mult;
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| 65 |
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| 66 | if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
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| 67 | xhci_ep->isoch_max_size = desc->usb3.bytes_per_interval
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| 68 | ? desc->usb3.bytes_per_interval
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| 69 | : desc->max_packet_size * (desc->packets + 1);
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| 70 | /* Technically there could be superspeed plus too. */
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| 71 |
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| 72 | /* Allocate and setup isochronous-specific structures. */
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| 73 | xhci_ep->isoch_enqueue = 0;
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| 74 | xhci_ep->isoch_dequeue = XHCI_ISOCH_BUFFER_COUNT - 1;
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| 75 | xhci_ep->isoch_started = false;
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| 76 |
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| 77 | fibril_mutex_initialize(&xhci_ep->isoch_guard);
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| 78 | fibril_condvar_initialize(&xhci_ep->isoch_avail);
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| 79 | }
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| 80 |
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| 81 | return EOK;
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| 82 | }
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| 83 |
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| 84 | /** Finalize XHCI endpoint.
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| 85 | * @param[in] xhci_ep XHCI endpoint to finalize.
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| 86 | */
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| 87 | void xhci_endpoint_fini(xhci_endpoint_t *xhci_ep)
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| 88 | {
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| 89 | assert(xhci_ep);
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| 90 |
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| 91 | // TODO: Something missed?
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| 92 | }
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| 93 |
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| 94 | /** Determine the type of a XHCI endpoint.
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| 95 | * @param[in] ep XHCI endpoint to query.
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| 96 | *
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| 97 | * @return EP_TYPE_[CONTROL|ISOCH|BULK|INTERRUPT]_[IN|OUT]
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| 98 | */
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| 99 | static int xhci_endpoint_type(xhci_endpoint_t *ep)
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| 100 | {
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| 101 | const bool in = ep->base.direction == USB_DIRECTION_IN;
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| 102 |
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| 103 | switch (ep->base.transfer_type) {
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| 104 | case USB_TRANSFER_CONTROL:
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| 105 | return EP_TYPE_CONTROL;
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| 106 |
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| 107 | case USB_TRANSFER_ISOCHRONOUS:
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| 108 | return in ? EP_TYPE_ISOCH_IN
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| 109 | : EP_TYPE_ISOCH_OUT;
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| 110 |
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| 111 | case USB_TRANSFER_BULK:
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| 112 | return in ? EP_TYPE_BULK_IN
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| 113 | : EP_TYPE_BULK_OUT;
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| 114 |
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| 115 | case USB_TRANSFER_INTERRUPT:
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| 116 | return in ? EP_TYPE_INTERRUPT_IN
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| 117 | : EP_TYPE_INTERRUPT_OUT;
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| 118 | }
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| 119 |
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| 120 | return EP_TYPE_INVALID;
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| 121 | }
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| 122 |
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| 123 | /** Test whether an XHCI endpoint uses streams.
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| 124 | * @param[in] xhci_ep XHCI endpoint to query.
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| 125 | *
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| 126 | * @return True if the endpoint uses streams.
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| 127 | */
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| 128 | static bool endpoint_using_streams(xhci_endpoint_t *xhci_ep)
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| 129 | {
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| 130 | return xhci_ep->primary_stream_ctx_array != NULL;
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| 131 | }
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| 132 |
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| 133 | /** Determine maximum size of XHCI endpoint's Primary Stream Context Array.
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| 134 | * @param[in] xhci_ep XHCI endpoint to query.
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| 135 | *
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| 136 | * @return Number of items in the Primary Stream Context Array.
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| 137 | */
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| 138 | static size_t primary_stream_ctx_array_max_size(xhci_endpoint_t *xhci_ep)
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| 139 | {
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| 140 | if (!xhci_ep->max_streams)
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| 141 | return 0;
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| 142 |
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| 143 | /* Section 6.2.3, Table 61 */
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| 144 | return 1 << (xhci_ep->max_streams + 1);
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| 145 | }
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| 146 |
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| 147 | // static bool primary_stream_ctx_has_secondary_array(xhci_stream_ctx_t *primary_ctx) {
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| 148 | // /* Section 6.2.4.1, SCT values */
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| 149 | // return XHCI_STREAM_SCT(*primary_ctx) >= 2;
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| 150 | // }
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| 151 | //
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| 152 | // static size_t secondary_stream_ctx_array_size(xhci_stream_ctx_t *primary_ctx) {
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| 153 | // if (XHCI_STREAM_SCT(*primary_ctx) < 2) return 0;
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| 154 | // return 2 << XHCI_STREAM_SCT(*primary_ctx);
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| 155 | // }
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| 156 |
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| 157 | /** Initialize primary streams of XHCI bulk endpoint.
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| 158 | * @param[in] hc Host controller of the endpoint.
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| 159 | * @param[in] xhci_epi XHCI bulk endpoint to use.
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| 160 | * @param[in] count Number of primary streams to initialize.
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| 161 | */
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| 162 | static void initialize_primary_streams(xhci_hc_t *hc, xhci_endpoint_t *xhci_ep, unsigned count) {
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| 163 | for (size_t index = 0; index < count; ++index) {
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| 164 | xhci_stream_ctx_t *ctx = &xhci_ep->primary_stream_ctx_array[index];
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| 165 | xhci_trb_ring_t *ring = &xhci_ep->primary_stream_rings[index];
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| 166 |
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| 167 | /* Init and register TRB ring for every primary stream */
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| 168 | xhci_trb_ring_init(ring); // FIXME: Not checking error code?
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| 169 | XHCI_STREAM_DEQ_PTR_SET(*ctx, ring->dequeue);
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| 170 |
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| 171 | /* Set to linear stream array */
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| 172 | XHCI_STREAM_SCT_SET(*ctx, 1);
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| 173 | }
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| 174 | }
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| 175 |
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| 176 | /** Configure XHCI bulk endpoint's stream context.
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| 177 | * @param[in] xhci_ep Associated XHCI bulk endpoint.
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| 178 | * @param[in] ctx Endpoint context to configure.
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| 179 | * @param[in] pstreams The value of MaxPStreams.
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| 180 | */
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| 181 | static void setup_stream_context(xhci_endpoint_t *xhci_ep, xhci_ep_ctx_t *ctx, unsigned pstreams) {
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| 182 | XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(xhci_ep));
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| 183 | XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, xhci_ep->base.max_packet_size);
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| 184 | XHCI_EP_MAX_BURST_SIZE_SET(*ctx, xhci_ep->max_burst);
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| 185 | XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
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| 186 |
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| 187 | XHCI_EP_MAX_P_STREAMS_SET(*ctx, pstreams);
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| 188 | XHCI_EP_TR_DPTR_SET(*ctx, xhci_ep->primary_stream_ctx_dma.phys);
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| 189 | // TODO: set HID?
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| 190 | XHCI_EP_LSA_SET(*ctx, 1);
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| 191 | }
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| 192 |
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| 193 | /** TODO document this
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| 194 | */
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| 195 | int xhci_endpoint_request_streams(xhci_hc_t *hc, xhci_device_t *dev, xhci_endpoint_t *xhci_ep, unsigned count) {
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| 196 | if (xhci_ep->base.transfer_type != USB_TRANSFER_BULK
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| 197 | || dev->base.speed != USB_SPEED_SUPER) {
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| 198 | usb_log_error("Streams are only supported by superspeed bulk endpoints.");
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| 199 | return EINVAL;
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| 200 | }
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| 201 |
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| 202 | if (!primary_stream_ctx_array_max_size(xhci_ep)) {
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| 203 | usb_log_error("Streams are not supported by endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
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| 204 | return EINVAL;
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| 205 | }
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| 206 |
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| 207 | uint8_t max_psa_size = 2 << XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_PSA_SIZE);
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| 208 | if (count > max_psa_size) {
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| 209 | // FIXME: We don't support secondary stream arrays yet, so we just give up for this
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| 210 | return ENOTSUP;
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| 211 | }
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| 212 |
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| 213 | if (count > (unsigned) (1 << xhci_ep->max_streams)) {
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| 214 | usb_log_error("Endpoint " XHCI_EP_FMT " supports only %u streams.",
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| 215 | XHCI_EP_ARGS(*xhci_ep), (1 << xhci_ep->max_streams));
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| 216 | return EINVAL;
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| 217 | }
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| 218 |
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| 219 | if (count <= 1024) {
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| 220 | usb_log_debug2("Allocating primary stream context array of size %u for endpoint " XHCI_EP_FMT,
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| 221 | count, XHCI_EP_ARGS(*xhci_ep));
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| 222 | if ((dma_buffer_alloc(&xhci_ep->primary_stream_ctx_dma, count * sizeof(xhci_stream_ctx_t))))
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| 223 | return ENOMEM;
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| 224 | xhci_ep->primary_stream_ctx_array = xhci_ep->primary_stream_ctx_dma.virt;
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| 225 |
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| 226 | xhci_ep->primary_stream_rings = calloc(count, sizeof(xhci_trb_ring_t));
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| 227 | if (!xhci_ep->primary_stream_rings) {
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| 228 | dma_buffer_free(&xhci_ep->primary_stream_ctx_dma);
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| 229 | return ENOMEM;
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| 230 | }
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| 231 |
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| 232 | // FIXME: count should be rounded to nearest power of 2 for xHC, workaround for now
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| 233 | count = 1024;
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| 234 | // FIXME: pstreams are "log2(count) - 1"
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| 235 | const size_t pstreams = 9;
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| 236 | xhci_ep->primary_stream_ctx_array_size = count;
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| 237 |
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| 238 | memset(xhci_ep->primary_stream_ctx_array, 0, count * sizeof(xhci_stream_ctx_t));
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| 239 | initialize_primary_streams(hc, xhci_ep, count);
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| 240 |
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| 241 | xhci_ep_ctx_t ep_ctx;
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| 242 | setup_stream_context(xhci_ep, &ep_ctx, pstreams);
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| 243 | return hc_add_endpoint(hc, dev->slot_id, xhci_endpoint_index(xhci_ep), &ep_ctx);
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| 244 | }
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| 245 | // FIXME: Complex stuff not supported yet
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| 246 | return ENOTSUP;
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| 247 | }
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| 248 |
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| 249 | /** TODO document this
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| 250 | */
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| 251 | static int xhci_isoch_alloc_transfers(xhci_endpoint_t *xhci_ep) {
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| 252 | int i = 0;
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| 253 | int err = EOK;
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| 254 | while (i < XHCI_ISOCH_BUFFER_COUNT) {
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| 255 | xhci_isoch_transfer_t *transfer = &xhci_ep->isoch_transfers[i];
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| 256 | if (dma_buffer_alloc(&transfer->data, xhci_ep->isoch_max_size)) {
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| 257 | err = ENOMEM;
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| 258 | break;
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| 259 | }
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| 260 | transfer->size = 0;
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| 261 | ++i;
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| 262 | }
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| 263 |
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| 264 | if (err) {
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| 265 | --i;
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| 266 | while(i >= 0) {
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| 267 | dma_buffer_free(&xhci_ep->isoch_transfers[i].data);
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| 268 | --i;
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| 269 | }
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| 270 | }
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| 271 |
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| 272 | return err;
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| 273 | }
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| 274 |
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| 275 | /** Allocate transfer data structures for XHCI endpoint.
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| 276 | * @param[in] xhci_ep XHCI endpoint to allocate data structures for.
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| 277 | *
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| 278 | * @return Error code.
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| 279 | */
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| 280 | int xhci_endpoint_alloc_transfer_ds(xhci_endpoint_t *xhci_ep)
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| 281 | {
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| 282 | /* Can't use XHCI_EP_FMT because the endpoint may not have device. */
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| 283 | usb_log_debug2("Allocating main transfer ring for endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
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| 284 |
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| 285 | xhci_ep->primary_stream_ctx_array = NULL;
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| 286 |
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| 287 | int err;
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| 288 | if ((err = xhci_trb_ring_init(&xhci_ep->ring))) {
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| 289 | return err;
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| 290 | }
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| 291 |
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| 292 | if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
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| 293 | if ((err = xhci_isoch_alloc_transfers(xhci_ep))) {
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| 294 | xhci_trb_ring_fini(&xhci_ep->ring);
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| 295 | return err;
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| 296 | }
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| 297 | }
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| 298 |
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| 299 | return EOK;
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| 300 | }
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| 301 |
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| 302 | /** Free transfer data structures for XHCI endpoint.
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| 303 | * @param[in] xhci_ep XHCI endpoint to free data structures for.
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| 304 | */
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| 305 | void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *xhci_ep)
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| 306 | {
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| 307 | if (endpoint_using_streams(xhci_ep)) {
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| 308 | usb_log_debug2("Freeing primary stream context array of endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
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| 309 |
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| 310 | // maybe check if LSA, then skip?
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| 311 | // for (size_t index = 0; index < primary_stream_ctx_array_size(xhci_ep); ++index) {
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| 312 | // xhci_stream_ctx_t *primary_ctx = xhci_ep->primary_stream_ctx_array + index;
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| 313 | // if (primary_stream_ctx_has_secondary_array(primary_ctx)) {
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| 314 | // // uintptr_t phys = XHCI_STREAM_DEQ_PTR(*primary_ctx);
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| 315 | // /* size_t size = */ secondary_stream_ctx_array_size(primary_ctx);
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| 316 | // // TODO: somehow map the address to virtual and free the secondary array
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| 317 | // }
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| 318 | // }
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| 319 | for (size_t index = 0; index < xhci_ep->primary_stream_ctx_array_size; ++index) {
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| 320 | // FIXME: Get the trb ring associated with stream [index] and fini it
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| 321 | }
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| 322 | dma_buffer_free(&xhci_ep->primary_stream_ctx_dma);
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| 323 | } else {
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| 324 | usb_log_debug2("Freeing main transfer ring of endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
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| 325 |
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| 326 | xhci_trb_ring_fini(&xhci_ep->ring);
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| 327 | }
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| 328 |
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| 329 | if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
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| 330 | for (size_t i = 0; i < XHCI_ISOCH_BUFFER_COUNT; ++i) {
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| 331 | dma_buffer_free(&xhci_ep->isoch_transfers[i].data);
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| 332 | }
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| 333 | }
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| 334 | }
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| 335 |
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| 336 | /** See section 4.5.1 of the xHCI spec.
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| 337 | */
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| 338 | uint8_t xhci_endpoint_dci(xhci_endpoint_t *ep)
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| 339 | {
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| 340 | return (2 * ep->base.endpoint) +
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| 341 | (ep->base.transfer_type == USB_TRANSFER_CONTROL
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| 342 | || ep->base.direction == USB_DIRECTION_IN);
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| 343 | }
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| 344 |
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| 345 | /** Return an index to the endpoint array. The indices are assigned as follows:
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| 346 | * 0 EP0 BOTH
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| 347 | * 1 EP1 OUT
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| 348 | * 2 EP1 IN
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| 349 | *
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| 350 | * For control endpoints >0, the IN endpoint index is used.
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| 351 | *
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| 352 | * The index returned must be usually offset by a number of contexts preceding
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| 353 | * the endpoint contexts themselves.
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| 354 | */
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| 355 | uint8_t xhci_endpoint_index(xhci_endpoint_t *ep)
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| 356 | {
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| 357 | return xhci_endpoint_dci(ep) - 1;
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| 358 | }
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| 359 |
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| 360 | /** Configure endpoint context of a control endpoint.
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| 361 | * @param[in] ep XHCI control endpoint.
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| 362 | * @param[in] ctx Endpoint context to configure.
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| 363 | */
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| 364 | static void setup_control_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
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| 365 | {
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| 366 | XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
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| 367 | XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
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| 368 | XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
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| 369 | XHCI_EP_MULT_SET(*ctx, ep->mult);
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| 370 | XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
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| 371 | XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
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| 372 | XHCI_EP_DCS_SET(*ctx, 1);
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| 373 | }
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| 374 |
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| 375 | /** Configure endpoint context of a bulk endpoint.
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| 376 | * @param[in] ep XHCI bulk endpoint.
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| 377 | * @param[in] ctx Endpoint context to configure.
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| 378 | */
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| 379 | static void setup_bulk_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
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| 380 | {
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| 381 | XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
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| 382 | XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
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| 383 | XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
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| 384 | XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
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| 385 |
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| 386 | XHCI_EP_MAX_P_STREAMS_SET(*ctx, 0);
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| 387 | XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
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| 388 | XHCI_EP_DCS_SET(*ctx, 1);
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| 389 | }
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| 390 |
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| 391 | /** Configure endpoint context of a isochronous endpoint.
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| 392 | * @param[in] ep XHCI isochronous endpoint.
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| 393 | * @param[in] ctx Endpoint context to configure.
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| 394 | */
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| 395 | static void setup_isoch_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
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| 396 | {
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| 397 | XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
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| 398 | XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
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| 399 | XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
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| 400 | XHCI_EP_MULT_SET(*ctx, ep->mult);
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| 401 | XHCI_EP_ERROR_COUNT_SET(*ctx, 0);
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| 402 | XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
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| 403 | XHCI_EP_DCS_SET(*ctx, 1);
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| 404 |
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| 405 | XHCI_EP_MAX_ESIT_PAYLOAD_LO_SET(*ctx, ep->isoch_max_size & 0xFFFF);
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| 406 | XHCI_EP_MAX_ESIT_PAYLOAD_HI_SET(*ctx, (ep->isoch_max_size >> 16) & 0xFF);
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| 407 | }
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| 408 |
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| 409 | /** Configure endpoint context of a interrupt endpoint.
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| 410 | * @param[in] ep XHCI interrupt endpoint.
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| 411 | * @param[in] ctx Endpoint context to configure.
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| 412 | */
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| 413 | static void setup_interrupt_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
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| 414 | {
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| 415 | XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
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| 416 | XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
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| 417 | XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
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| 418 | XHCI_EP_MULT_SET(*ctx, 0);
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| 419 | XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
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| 420 | XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
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| 421 | XHCI_EP_DCS_SET(*ctx, 1);
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| 422 | // TODO: max ESIT payload
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| 423 | }
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| 424 |
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| 425 | /** Type of endpoint context configuration function. */
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| 426 | typedef void (*setup_ep_ctx_helper)(xhci_endpoint_t *, xhci_ep_ctx_t *);
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| 427 |
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| 428 | /** Static array, which maps USB endpoint types to their respective endpoint context configuration functions. */
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| 429 | static const setup_ep_ctx_helper setup_ep_ctx_helpers[] = {
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| 430 | [USB_TRANSFER_CONTROL] = setup_control_ep_ctx,
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| 431 | [USB_TRANSFER_ISOCHRONOUS] = setup_isoch_ep_ctx,
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| 432 | [USB_TRANSFER_BULK] = setup_bulk_ep_ctx,
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| 433 | [USB_TRANSFER_INTERRUPT] = setup_interrupt_ep_ctx,
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| 434 | };
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| 435 |
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| 436 | /** Configure endpoint context of XHCI endpoint.
|
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| 437 | * @param[in] ep Associated XHCI endpoint.
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| 438 | * @param[in] ep_ctx Endpoint context to configure.
|
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| 439 | */
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| 440 | void xhci_setup_endpoint_context(xhci_endpoint_t *ep, xhci_ep_ctx_t *ep_ctx)
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| 441 | {
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| 442 | assert(ep);
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| 443 | assert(ep_ctx);
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| 444 |
|
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| 445 | usb_transfer_type_t tt = ep->base.transfer_type;
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| 446 | assert(tt < ARRAY_SIZE(setup_ep_ctx_helpers));
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| 447 |
|
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| 448 | memset(ep_ctx, 0, sizeof(*ep_ctx));
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| 449 | setup_ep_ctx_helpers[tt](ep, ep_ctx);
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| 450 | }
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| 451 |
|
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| 452 | /** Add a new XHCI endpoint to a device. The device must be online unless
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| 453 | * the added endpoint is number 0.
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| 454 | * @param[in] dev XHCI device, to which to add the endpoint
|
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| 455 | * @param[in] ep XHCI endpoint to add.
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| 456 | *
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| 457 | * @return Error code.
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| 458 | */
|
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| 459 | int xhci_device_add_endpoint(xhci_device_t *dev, xhci_endpoint_t *ep)
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| 460 | {
|
|---|
| 461 | assert(dev);
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|---|
| 462 | assert(ep);
|
|---|
| 463 |
|
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| 464 | /* Offline devices don't create new endpoints other than EP0. */
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|---|
| 465 | if (!dev->online && ep->base.endpoint > 0) {
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| 466 | return EAGAIN;
|
|---|
| 467 | }
|
|---|
| 468 |
|
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| 469 | const usb_endpoint_t ep_num = ep->base.endpoint;
|
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| 470 |
|
|---|
| 471 | if (dev->endpoints[ep_num])
|
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| 472 | return EEXIST;
|
|---|
| 473 |
|
|---|
| 474 | /* Device reference */
|
|---|
| 475 | endpoint_add_ref(&ep->base);
|
|---|
| 476 | ep->base.device = &dev->base;
|
|---|
| 477 | dev->endpoints[ep_num] = ep;
|
|---|
| 478 |
|
|---|
| 479 | return EOK;
|
|---|
| 480 | }
|
|---|
| 481 |
|
|---|
| 482 | /** Remove XHCI endpoint from a device.
|
|---|
| 483 | * @param[in] ep XHCI endpoint to remove.
|
|---|
| 484 | */
|
|---|
| 485 | void xhci_device_remove_endpoint(xhci_endpoint_t *ep)
|
|---|
| 486 | {
|
|---|
| 487 | assert(ep);
|
|---|
| 488 | xhci_device_t *dev = xhci_device_get(ep->base.device);
|
|---|
| 489 |
|
|---|
| 490 | assert(dev->endpoints[ep->base.endpoint]);
|
|---|
| 491 | dev->endpoints[ep->base.endpoint] = NULL;
|
|---|
| 492 | ep->base.device = NULL;
|
|---|
| 493 |
|
|---|
| 494 | endpoint_del_ref(&ep->base);
|
|---|
| 495 | }
|
|---|
| 496 |
|
|---|
| 497 | /** Retrieve XHCI endpoint from a device by the endpoint number.
|
|---|
| 498 | * @param[in] dev XHCI device to query.
|
|---|
| 499 | * @param[in] ep Endpoint number identifying the endpoint to retrieve.
|
|---|
| 500 | *
|
|---|
| 501 | * @return XHCI endpoint with the specified number or NULL if no such endpoint exists.
|
|---|
| 502 | */
|
|---|
| 503 | xhci_endpoint_t *xhci_device_get_endpoint(xhci_device_t *dev, usb_endpoint_t ep)
|
|---|
| 504 | {
|
|---|
| 505 | return dev->endpoints[ep];
|
|---|
| 506 | }
|
|---|
| 507 |
|
|---|
| 508 | /**
|
|---|
| 509 | * @}
|
|---|
| 510 | */
|
|---|