source: mainline/uspace/drv/bus/usb/xhci/endpoint.c@ 95a62dc

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 95a62dc was 2e2af3a, checked in by Petr Manek <petr.manek@…>, 8 years ago

xhci: add docstrings in endpoint.c

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1/*
2 * Copyright (c) 2017 Petr Manek
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller endpoint management.
34 */
35
36#include <usb/host/endpoint.h>
37#include <usb/descriptor.h>
38
39#include <errno.h>
40#include <macros.h>
41
42#include "hc.h"
43#include "bus.h"
44#include "commands.h"
45#include "endpoint.h"
46
47/** Initialize new XHCI endpoint.
48 * @param[in] xhci_ep Allocated XHCI endpoint to initialize.
49 * @param[in] dev Device, to which the endpoint belongs.
50 * @param[in] desc USB endpoint descriptor carrying configuration data.
51 *
52 * @return Error code.
53 */
54int xhci_endpoint_init(xhci_endpoint_t *xhci_ep, device_t *dev, const usb_endpoint_desc_t *desc)
55{
56 assert(xhci_ep);
57
58 endpoint_t *ep = &xhci_ep->base;
59
60 endpoint_init(ep, dev, desc);
61
62 xhci_ep->max_streams = desc->usb3.max_streams;
63 xhci_ep->max_burst = desc->usb3.max_burst;
64 xhci_ep->mult = desc->usb3.mult;
65
66 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
67 xhci_ep->isoch_max_size = desc->usb3.bytes_per_interval
68 ? desc->usb3.bytes_per_interval
69 : desc->max_packet_size * (desc->packets + 1);
70 /* Technically there could be superspeed plus too. */
71
72 /* Allocate and setup isochronous-specific structures. */
73 xhci_ep->isoch_enqueue = 0;
74 xhci_ep->isoch_dequeue = XHCI_ISOCH_BUFFER_COUNT - 1;
75 xhci_ep->isoch_started = false;
76
77 fibril_mutex_initialize(&xhci_ep->isoch_guard);
78 fibril_condvar_initialize(&xhci_ep->isoch_avail);
79 }
80
81 return EOK;
82}
83
84/** Finalize XHCI endpoint.
85 * @param[in] xhci_ep XHCI endpoint to finalize.
86 */
87void xhci_endpoint_fini(xhci_endpoint_t *xhci_ep)
88{
89 assert(xhci_ep);
90
91 // TODO: Something missed?
92}
93
94/** Determine the type of a XHCI endpoint.
95 * @param[in] ep XHCI endpoint to query.
96 *
97 * @return EP_TYPE_[CONTROL|ISOCH|BULK|INTERRUPT]_[IN|OUT]
98 */
99static int xhci_endpoint_type(xhci_endpoint_t *ep)
100{
101 const bool in = ep->base.direction == USB_DIRECTION_IN;
102
103 switch (ep->base.transfer_type) {
104 case USB_TRANSFER_CONTROL:
105 return EP_TYPE_CONTROL;
106
107 case USB_TRANSFER_ISOCHRONOUS:
108 return in ? EP_TYPE_ISOCH_IN
109 : EP_TYPE_ISOCH_OUT;
110
111 case USB_TRANSFER_BULK:
112 return in ? EP_TYPE_BULK_IN
113 : EP_TYPE_BULK_OUT;
114
115 case USB_TRANSFER_INTERRUPT:
116 return in ? EP_TYPE_INTERRUPT_IN
117 : EP_TYPE_INTERRUPT_OUT;
118 }
119
120 return EP_TYPE_INVALID;
121}
122
123/** Test whether an XHCI endpoint uses streams.
124 * @param[in] xhci_ep XHCI endpoint to query.
125 *
126 * @return True if the endpoint uses streams.
127 */
128static bool endpoint_using_streams(xhci_endpoint_t *xhci_ep)
129{
130 return xhci_ep->primary_stream_ctx_array != NULL;
131}
132
133/** Determine maximum size of XHCI endpoint's Primary Stream Context Array.
134 * @param[in] xhci_ep XHCI endpoint to query.
135 *
136 * @return Number of items in the Primary Stream Context Array.
137 */
138static size_t primary_stream_ctx_array_max_size(xhci_endpoint_t *xhci_ep)
139{
140 if (!xhci_ep->max_streams)
141 return 0;
142
143 /* Section 6.2.3, Table 61 */
144 return 1 << (xhci_ep->max_streams + 1);
145}
146
147// static bool primary_stream_ctx_has_secondary_array(xhci_stream_ctx_t *primary_ctx) {
148// /* Section 6.2.4.1, SCT values */
149// return XHCI_STREAM_SCT(*primary_ctx) >= 2;
150// }
151//
152// static size_t secondary_stream_ctx_array_size(xhci_stream_ctx_t *primary_ctx) {
153// if (XHCI_STREAM_SCT(*primary_ctx) < 2) return 0;
154// return 2 << XHCI_STREAM_SCT(*primary_ctx);
155// }
156
157/** Initialize primary streams of XHCI bulk endpoint.
158 * @param[in] hc Host controller of the endpoint.
159 * @param[in] xhci_epi XHCI bulk endpoint to use.
160 * @param[in] count Number of primary streams to initialize.
161 */
162static void initialize_primary_streams(xhci_hc_t *hc, xhci_endpoint_t *xhci_ep, unsigned count) {
163 for (size_t index = 0; index < count; ++index) {
164 xhci_stream_ctx_t *ctx = &xhci_ep->primary_stream_ctx_array[index];
165 xhci_trb_ring_t *ring = &xhci_ep->primary_stream_rings[index];
166
167 /* Init and register TRB ring for every primary stream */
168 xhci_trb_ring_init(ring); // FIXME: Not checking error code?
169 XHCI_STREAM_DEQ_PTR_SET(*ctx, ring->dequeue);
170
171 /* Set to linear stream array */
172 XHCI_STREAM_SCT_SET(*ctx, 1);
173 }
174}
175
176/** Configure XHCI bulk endpoint's stream context.
177 * @param[in] xhci_ep Associated XHCI bulk endpoint.
178 * @param[in] ctx Endpoint context to configure.
179 * @param[in] pstreams The value of MaxPStreams.
180 */
181static void setup_stream_context(xhci_endpoint_t *xhci_ep, xhci_ep_ctx_t *ctx, unsigned pstreams) {
182 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(xhci_ep));
183 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, xhci_ep->base.max_packet_size);
184 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, xhci_ep->max_burst);
185 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
186
187 XHCI_EP_MAX_P_STREAMS_SET(*ctx, pstreams);
188 XHCI_EP_TR_DPTR_SET(*ctx, xhci_ep->primary_stream_ctx_dma.phys);
189 // TODO: set HID?
190 XHCI_EP_LSA_SET(*ctx, 1);
191}
192
193/** TODO document this
194 */
195int xhci_endpoint_request_streams(xhci_hc_t *hc, xhci_device_t *dev, xhci_endpoint_t *xhci_ep, unsigned count) {
196 if (xhci_ep->base.transfer_type != USB_TRANSFER_BULK
197 || dev->base.speed != USB_SPEED_SUPER) {
198 usb_log_error("Streams are only supported by superspeed bulk endpoints.");
199 return EINVAL;
200 }
201
202 if (!primary_stream_ctx_array_max_size(xhci_ep)) {
203 usb_log_error("Streams are not supported by endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
204 return EINVAL;
205 }
206
207 uint8_t max_psa_size = 2 << XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_PSA_SIZE);
208 if (count > max_psa_size) {
209 // FIXME: We don't support secondary stream arrays yet, so we just give up for this
210 return ENOTSUP;
211 }
212
213 if (count > (unsigned) (1 << xhci_ep->max_streams)) {
214 usb_log_error("Endpoint " XHCI_EP_FMT " supports only %u streams.",
215 XHCI_EP_ARGS(*xhci_ep), (1 << xhci_ep->max_streams));
216 return EINVAL;
217 }
218
219 if (count <= 1024) {
220 usb_log_debug2("Allocating primary stream context array of size %u for endpoint " XHCI_EP_FMT,
221 count, XHCI_EP_ARGS(*xhci_ep));
222 if ((dma_buffer_alloc(&xhci_ep->primary_stream_ctx_dma, count * sizeof(xhci_stream_ctx_t))))
223 return ENOMEM;
224 xhci_ep->primary_stream_ctx_array = xhci_ep->primary_stream_ctx_dma.virt;
225
226 xhci_ep->primary_stream_rings = calloc(count, sizeof(xhci_trb_ring_t));
227 if (!xhci_ep->primary_stream_rings) {
228 dma_buffer_free(&xhci_ep->primary_stream_ctx_dma);
229 return ENOMEM;
230 }
231
232 // FIXME: count should be rounded to nearest power of 2 for xHC, workaround for now
233 count = 1024;
234 // FIXME: pstreams are "log2(count) - 1"
235 const size_t pstreams = 9;
236 xhci_ep->primary_stream_ctx_array_size = count;
237
238 memset(xhci_ep->primary_stream_ctx_array, 0, count * sizeof(xhci_stream_ctx_t));
239 initialize_primary_streams(hc, xhci_ep, count);
240
241 xhci_ep_ctx_t ep_ctx;
242 setup_stream_context(xhci_ep, &ep_ctx, pstreams);
243 return hc_add_endpoint(hc, dev->slot_id, xhci_endpoint_index(xhci_ep), &ep_ctx);
244 }
245 // FIXME: Complex stuff not supported yet
246 return ENOTSUP;
247}
248
249/** TODO document this
250 */
251static int xhci_isoch_alloc_transfers(xhci_endpoint_t *xhci_ep) {
252 int i = 0;
253 int err = EOK;
254 while (i < XHCI_ISOCH_BUFFER_COUNT) {
255 xhci_isoch_transfer_t *transfer = &xhci_ep->isoch_transfers[i];
256 if (dma_buffer_alloc(&transfer->data, xhci_ep->isoch_max_size)) {
257 err = ENOMEM;
258 break;
259 }
260 transfer->size = 0;
261 ++i;
262 }
263
264 if (err) {
265 --i;
266 while(i >= 0) {
267 dma_buffer_free(&xhci_ep->isoch_transfers[i].data);
268 --i;
269 }
270 }
271
272 return err;
273}
274
275/** Allocate transfer data structures for XHCI endpoint.
276 * @param[in] xhci_ep XHCI endpoint to allocate data structures for.
277 *
278 * @return Error code.
279 */
280int xhci_endpoint_alloc_transfer_ds(xhci_endpoint_t *xhci_ep)
281{
282 /* Can't use XHCI_EP_FMT because the endpoint may not have device. */
283 usb_log_debug2("Allocating main transfer ring for endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
284
285 xhci_ep->primary_stream_ctx_array = NULL;
286
287 int err;
288 if ((err = xhci_trb_ring_init(&xhci_ep->ring))) {
289 return err;
290 }
291
292 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
293 if ((err = xhci_isoch_alloc_transfers(xhci_ep))) {
294 xhci_trb_ring_fini(&xhci_ep->ring);
295 return err;
296 }
297 }
298
299 return EOK;
300}
301
302/** Free transfer data structures for XHCI endpoint.
303 * @param[in] xhci_ep XHCI endpoint to free data structures for.
304 */
305void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *xhci_ep)
306{
307 if (endpoint_using_streams(xhci_ep)) {
308 usb_log_debug2("Freeing primary stream context array of endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
309
310 // maybe check if LSA, then skip?
311 // for (size_t index = 0; index < primary_stream_ctx_array_size(xhci_ep); ++index) {
312 // xhci_stream_ctx_t *primary_ctx = xhci_ep->primary_stream_ctx_array + index;
313 // if (primary_stream_ctx_has_secondary_array(primary_ctx)) {
314 // // uintptr_t phys = XHCI_STREAM_DEQ_PTR(*primary_ctx);
315 // /* size_t size = */ secondary_stream_ctx_array_size(primary_ctx);
316 // // TODO: somehow map the address to virtual and free the secondary array
317 // }
318 // }
319 for (size_t index = 0; index < xhci_ep->primary_stream_ctx_array_size; ++index) {
320 // FIXME: Get the trb ring associated with stream [index] and fini it
321 }
322 dma_buffer_free(&xhci_ep->primary_stream_ctx_dma);
323 } else {
324 usb_log_debug2("Freeing main transfer ring of endpoint " XHCI_EP_FMT, XHCI_EP_ARGS(*xhci_ep));
325
326 xhci_trb_ring_fini(&xhci_ep->ring);
327 }
328
329 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
330 for (size_t i = 0; i < XHCI_ISOCH_BUFFER_COUNT; ++i) {
331 dma_buffer_free(&xhci_ep->isoch_transfers[i].data);
332 }
333 }
334}
335
336/** See section 4.5.1 of the xHCI spec.
337 */
338uint8_t xhci_endpoint_dci(xhci_endpoint_t *ep)
339{
340 return (2 * ep->base.endpoint) +
341 (ep->base.transfer_type == USB_TRANSFER_CONTROL
342 || ep->base.direction == USB_DIRECTION_IN);
343}
344
345/** Return an index to the endpoint array. The indices are assigned as follows:
346 * 0 EP0 BOTH
347 * 1 EP1 OUT
348 * 2 EP1 IN
349 *
350 * For control endpoints >0, the IN endpoint index is used.
351 *
352 * The index returned must be usually offset by a number of contexts preceding
353 * the endpoint contexts themselves.
354 */
355uint8_t xhci_endpoint_index(xhci_endpoint_t *ep)
356{
357 return xhci_endpoint_dci(ep) - 1;
358}
359
360/** Configure endpoint context of a control endpoint.
361 * @param[in] ep XHCI control endpoint.
362 * @param[in] ctx Endpoint context to configure.
363 */
364static void setup_control_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
365{
366 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
367 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
368 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
369 XHCI_EP_MULT_SET(*ctx, ep->mult);
370 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
371 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
372 XHCI_EP_DCS_SET(*ctx, 1);
373}
374
375/** Configure endpoint context of a bulk endpoint.
376 * @param[in] ep XHCI bulk endpoint.
377 * @param[in] ctx Endpoint context to configure.
378 */
379static void setup_bulk_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
380{
381 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
382 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
383 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
384 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
385
386 XHCI_EP_MAX_P_STREAMS_SET(*ctx, 0);
387 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
388 XHCI_EP_DCS_SET(*ctx, 1);
389}
390
391/** Configure endpoint context of a isochronous endpoint.
392 * @param[in] ep XHCI isochronous endpoint.
393 * @param[in] ctx Endpoint context to configure.
394 */
395static void setup_isoch_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
396{
397 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
398 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
399 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
400 XHCI_EP_MULT_SET(*ctx, ep->mult);
401 XHCI_EP_ERROR_COUNT_SET(*ctx, 0);
402 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
403 XHCI_EP_DCS_SET(*ctx, 1);
404
405 XHCI_EP_MAX_ESIT_PAYLOAD_LO_SET(*ctx, ep->isoch_max_size & 0xFFFF);
406 XHCI_EP_MAX_ESIT_PAYLOAD_HI_SET(*ctx, (ep->isoch_max_size >> 16) & 0xFF);
407}
408
409/** Configure endpoint context of a interrupt endpoint.
410 * @param[in] ep XHCI interrupt endpoint.
411 * @param[in] ctx Endpoint context to configure.
412 */
413static void setup_interrupt_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
414{
415 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
416 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
417 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst);
418 XHCI_EP_MULT_SET(*ctx, 0);
419 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
420 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
421 XHCI_EP_DCS_SET(*ctx, 1);
422 // TODO: max ESIT payload
423}
424
425/** Type of endpoint context configuration function. */
426typedef void (*setup_ep_ctx_helper)(xhci_endpoint_t *, xhci_ep_ctx_t *);
427
428/** Static array, which maps USB endpoint types to their respective endpoint context configuration functions. */
429static const setup_ep_ctx_helper setup_ep_ctx_helpers[] = {
430 [USB_TRANSFER_CONTROL] = setup_control_ep_ctx,
431 [USB_TRANSFER_ISOCHRONOUS] = setup_isoch_ep_ctx,
432 [USB_TRANSFER_BULK] = setup_bulk_ep_ctx,
433 [USB_TRANSFER_INTERRUPT] = setup_interrupt_ep_ctx,
434};
435
436/** Configure endpoint context of XHCI endpoint.
437 * @param[in] ep Associated XHCI endpoint.
438 * @param[in] ep_ctx Endpoint context to configure.
439 */
440void xhci_setup_endpoint_context(xhci_endpoint_t *ep, xhci_ep_ctx_t *ep_ctx)
441{
442 assert(ep);
443 assert(ep_ctx);
444
445 usb_transfer_type_t tt = ep->base.transfer_type;
446 assert(tt < ARRAY_SIZE(setup_ep_ctx_helpers));
447
448 memset(ep_ctx, 0, sizeof(*ep_ctx));
449 setup_ep_ctx_helpers[tt](ep, ep_ctx);
450}
451
452/** Add a new XHCI endpoint to a device. The device must be online unless
453 * the added endpoint is number 0.
454 * @param[in] dev XHCI device, to which to add the endpoint
455 * @param[in] ep XHCI endpoint to add.
456 *
457 * @return Error code.
458 */
459int xhci_device_add_endpoint(xhci_device_t *dev, xhci_endpoint_t *ep)
460{
461 assert(dev);
462 assert(ep);
463
464 /* Offline devices don't create new endpoints other than EP0. */
465 if (!dev->online && ep->base.endpoint > 0) {
466 return EAGAIN;
467 }
468
469 const usb_endpoint_t ep_num = ep->base.endpoint;
470
471 if (dev->endpoints[ep_num])
472 return EEXIST;
473
474 /* Device reference */
475 endpoint_add_ref(&ep->base);
476 ep->base.device = &dev->base;
477 dev->endpoints[ep_num] = ep;
478
479 return EOK;
480}
481
482/** Remove XHCI endpoint from a device.
483 * @param[in] ep XHCI endpoint to remove.
484 */
485void xhci_device_remove_endpoint(xhci_endpoint_t *ep)
486{
487 assert(ep);
488 xhci_device_t *dev = xhci_device_get(ep->base.device);
489
490 assert(dev->endpoints[ep->base.endpoint]);
491 dev->endpoints[ep->base.endpoint] = NULL;
492 ep->base.device = NULL;
493
494 endpoint_del_ref(&ep->base);
495}
496
497/** Retrieve XHCI endpoint from a device by the endpoint number.
498 * @param[in] dev XHCI device to query.
499 * @param[in] ep Endpoint number identifying the endpoint to retrieve.
500 *
501 * @return XHCI endpoint with the specified number or NULL if no such endpoint exists.
502 */
503xhci_endpoint_t *xhci_device_get_endpoint(xhci_device_t *dev, usb_endpoint_t ep)
504{
505 return dev->endpoints[ep];
506}
507
508/**
509 * @}
510 */
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