1 | /*
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2 | * Copyright (c) 2018 Petr Manek, Ondrej Hlavaty, Michal Staruch, Jan Hrach
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 |
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29 | /** @addtogroup drvusbxhci
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30 | * @{
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31 | */
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32 | /** @file
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33 | * @brief The host controller endpoint management.
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34 | */
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35 |
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36 | #include <usb/host/endpoint.h>
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37 | #include <usb/descriptor.h>
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38 |
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39 | #include <errno.h>
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40 | #include <macros.h>
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41 | #include <str_error.h>
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42 |
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43 | #include "hc.h"
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44 | #include "bus.h"
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45 | #include "commands.h"
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46 | #include "device.h"
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47 | #include "endpoint.h"
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48 | #include "streams.h"
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49 |
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50 | static errno_t alloc_transfer_ds(xhci_endpoint_t *);
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51 |
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52 | /**
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53 | * Initialize new XHCI endpoint.
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54 | * @param[in] xhci_ep Allocated XHCI endpoint to initialize.
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55 | * @param[in] dev Device, to which the endpoint belongs.
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56 | * @param[in] desc USB endpoint descriptor carrying configuration data.
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57 | *
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58 | * @return Error code.
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59 | */
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60 | static errno_t xhci_endpoint_init(xhci_endpoint_t *xhci_ep, device_t *dev,
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61 | const usb_endpoint_descriptors_t *desc)
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62 | {
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63 | errno_t rc;
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64 | assert(xhci_ep);
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65 |
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66 | endpoint_t *ep = &xhci_ep->base;
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67 |
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68 | endpoint_init(ep, dev, desc);
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69 |
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70 | fibril_mutex_initialize(&xhci_ep->guard);
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71 |
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72 | xhci_ep->max_burst = desc->companion.max_burst + 1;
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73 |
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74 | if (ep->transfer_type == USB_TRANSFER_BULK)
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75 | xhci_ep->max_streams = 1 << (USB_SSC_MAX_STREAMS(desc->companion));
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76 | else
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77 | xhci_ep->max_streams = 1;
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78 |
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79 | if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS)
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80 | xhci_ep->mult = USB_SSC_MULT(desc->companion) + 1;
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81 | else
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82 | xhci_ep->mult = 1;
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83 |
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84 | /*
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85 | * In USB 3, the semantics of wMaxPacketSize changed. Now the number of
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86 | * packets per service interval is determined from max_burst and mult.
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87 | */
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88 | if (dev->speed >= USB_SPEED_SUPER) {
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89 | ep->packets_per_uframe = xhci_ep->max_burst * xhci_ep->mult;
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90 | if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS ||
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91 | ep->transfer_type == USB_TRANSFER_INTERRUPT) {
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92 | ep->max_transfer_size = ep->max_packet_size * ep->packets_per_uframe;
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93 | }
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94 | }
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95 |
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96 | xhci_ep->interval = desc->endpoint.poll_interval;
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97 |
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98 | /*
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99 | * Only Low/Full speed interrupt endpoints have interval as a linear field,
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100 | * others have 2-based log of it.
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101 | */
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102 | if (dev->speed >= USB_SPEED_HIGH ||
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103 | ep->transfer_type != USB_TRANSFER_INTERRUPT) {
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104 |
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105 | // XXX: According to the spec, the interval should be
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106 | // from [1, 16]. However, in QEMU, we get 0 here
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107 | // (a QEMU bug?).
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108 | if (xhci_ep->interval == 0)
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109 | xhci_ep->interval = 8;
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110 |
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111 | xhci_ep->interval = 1 << (xhci_ep->interval - 1);
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112 | }
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113 |
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114 | /* Full speed devices have interval in frames */
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115 | if (dev->speed <= USB_SPEED_FULL) {
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116 | xhci_ep->interval *= 8;
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117 | }
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118 |
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119 | if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS)
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120 | isoch_init(xhci_ep, desc);
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121 |
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122 | if ((rc = alloc_transfer_ds(xhci_ep)))
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123 | goto err;
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124 |
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125 | unsigned flags = -1U;
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126 |
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127 | /* Some xHCs can handle 64-bit addresses */
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128 | xhci_bus_t *bus = bus_to_xhci_bus(ep->device->bus);
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129 | if (bus->hc->ac64)
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130 | flags &= ~DMA_POLICY_4GiB;
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131 |
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132 | /* xHCI works best if it can fit 65k transfers in one TRB */
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133 | ep->transfer_buffer_policy = dma_policy_create(flags, 1 << 16);
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134 |
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135 | /* But actualy can do full scatter-gather. */
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136 | ep->required_transfer_buffer_policy = dma_policy_create(flags, PAGE_SIZE);
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137 |
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138 | return EOK;
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139 |
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140 | err:
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141 | return rc;
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142 | }
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143 |
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144 | /**
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145 | * Create a new xHCI endpoint structure.
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146 | *
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147 | * Bus callback.
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148 | */
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149 | endpoint_t *xhci_endpoint_create(device_t *dev,
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150 | const usb_endpoint_descriptors_t *desc)
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151 | {
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152 | const usb_transfer_type_t type = USB_ED_GET_TRANSFER_TYPE(desc->endpoint);
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153 |
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154 | xhci_endpoint_t *ep = calloc(1, sizeof(xhci_endpoint_t) +
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155 | (type == USB_TRANSFER_ISOCHRONOUS) * sizeof(*ep->isoch));
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156 | if (!ep)
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157 | return NULL;
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158 |
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159 | if (xhci_endpoint_init(ep, dev, desc)) {
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160 | free(ep);
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161 | return NULL;
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162 | }
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163 |
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164 | return &ep->base;
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165 | }
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166 |
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167 | /**
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168 | * Finalize XHCI endpoint.
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169 | * @param[in] xhci_ep XHCI endpoint to finalize.
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170 | */
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171 | static void xhci_endpoint_fini(xhci_endpoint_t *xhci_ep)
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172 | {
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173 | assert(xhci_ep);
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174 |
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175 | xhci_endpoint_free_transfer_ds(xhci_ep);
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176 |
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177 | // TODO: Something missed?
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178 | }
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179 |
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180 | /**
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181 | * Destroy given xHCI endpoint structure.
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182 | *
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183 | * Bus callback.
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184 | */
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185 | void xhci_endpoint_destroy(endpoint_t *ep)
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186 | {
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187 | xhci_endpoint_t *xhci_ep = xhci_endpoint_get(ep);
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188 |
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189 | xhci_endpoint_fini(xhci_ep);
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190 | free(xhci_ep);
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191 | }
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192 |
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193 | /**
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194 | * Register an andpoint to the xHC.
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195 | *
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196 | * Bus callback.
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197 | */
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198 | errno_t xhci_endpoint_register(endpoint_t *ep_base)
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199 | {
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200 | errno_t err;
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201 | xhci_endpoint_t *ep = xhci_endpoint_get(ep_base);
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202 |
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203 | if (ep_base->endpoint != 0 && (err = hc_add_endpoint(ep)))
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204 | return err;
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205 |
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206 | endpoint_set_online(ep_base, &ep->guard);
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207 | return EOK;
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208 | }
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209 |
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210 | /**
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211 | * Abort a transfer on an endpoint.
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212 | */
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213 | static void endpoint_abort(endpoint_t *ep)
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214 | {
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215 | xhci_device_t *dev = xhci_device_get(ep->device);
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216 | xhci_endpoint_t *xhci_ep = xhci_endpoint_get(ep);
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217 |
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218 | /* This function can only abort endpoints without streams. */
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219 | assert(xhci_ep->primary_stream_data_array == NULL);
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220 |
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221 | fibril_mutex_lock(&xhci_ep->guard);
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222 |
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223 | endpoint_set_offline_locked(ep);
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224 |
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225 | if (!ep->active_batch) {
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226 | fibril_mutex_unlock(&xhci_ep->guard);
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227 | return;
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228 | }
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229 |
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230 | /* First, offer the batch a short chance to be finished. */
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231 | endpoint_wait_timeout_locked(ep, 10000);
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232 |
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233 | if (!ep->active_batch) {
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234 | fibril_mutex_unlock(&xhci_ep->guard);
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235 | return;
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236 | }
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237 |
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238 | usb_transfer_batch_t *const batch = ep->active_batch;
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239 |
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240 | const errno_t err = hc_stop_endpoint(xhci_ep);
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241 | if (err) {
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242 | usb_log_error("Failed to stop endpoint %u of device "
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243 | XHCI_DEV_FMT ": %s", ep->endpoint, XHCI_DEV_ARGS(*dev),
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244 | str_error(err));
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245 | }
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246 |
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247 | fibril_mutex_unlock(&xhci_ep->guard);
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248 |
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249 | batch->error = EINTR;
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250 | batch->transferred_size = 0;
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251 | usb_transfer_batch_finish(batch);
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252 | return;
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253 | }
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254 |
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255 | /**
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256 | * Unregister an endpoint. If the device is still available, inform the xHC
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257 | * about it.
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258 | *
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259 | * Bus callback.
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260 | */
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261 | void xhci_endpoint_unregister(endpoint_t *ep_base)
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262 | {
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263 | errno_t err;
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264 | xhci_endpoint_t *ep = xhci_endpoint_get(ep_base);
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265 | xhci_device_t *dev = xhci_device_get(ep_base->device);
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266 |
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267 | endpoint_abort(ep_base);
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268 |
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269 | /* If device slot is still available, drop the endpoint. */
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270 | if (ep_base->endpoint != 0 && dev->slot_id) {
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271 |
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272 | if ((err = hc_drop_endpoint(ep))) {
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273 | usb_log_error("Failed to drop endpoint " XHCI_EP_FMT ": %s",
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274 | XHCI_EP_ARGS(*ep), str_error(err));
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275 | }
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276 | } else {
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277 | usb_log_debug("Not going to drop endpoint " XHCI_EP_FMT " because"
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278 | " the slot has already been disabled.", XHCI_EP_ARGS(*ep));
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279 | }
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280 | }
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281 |
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282 | /**
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283 | * Determine the type of a XHCI endpoint.
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284 | * @param[in] ep XHCI endpoint to query.
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285 | *
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286 | * @return EP_TYPE_[CONTROL|ISOCH|BULK|INTERRUPT]_[IN|OUT]
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287 | */
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288 | int xhci_endpoint_type(xhci_endpoint_t *ep)
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289 | {
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290 | const bool in = ep->base.direction == USB_DIRECTION_IN;
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291 |
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292 | switch (ep->base.transfer_type) {
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293 | case USB_TRANSFER_CONTROL:
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294 | return EP_TYPE_CONTROL;
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295 |
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296 | case USB_TRANSFER_ISOCHRONOUS:
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297 | return in ? EP_TYPE_ISOCH_IN :
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298 | EP_TYPE_ISOCH_OUT;
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299 |
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300 | case USB_TRANSFER_BULK:
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301 | return in ? EP_TYPE_BULK_IN :
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302 | EP_TYPE_BULK_OUT;
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303 |
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304 | case USB_TRANSFER_INTERRUPT:
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305 | return in ? EP_TYPE_INTERRUPT_IN :
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306 | EP_TYPE_INTERRUPT_OUT;
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307 | }
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308 |
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309 | return EP_TYPE_INVALID;
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310 | }
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311 |
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312 | /**
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313 | * Allocate transfer data structures for XHCI endpoint not using streams.
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314 | * @param[in] xhci_ep XHCI endpoint to allocate data structures for.
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315 | *
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316 | * @return Error code.
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317 | */
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318 | static errno_t alloc_transfer_ds(xhci_endpoint_t *xhci_ep)
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319 | {
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320 | /* Can't use XHCI_EP_FMT because the endpoint may not have device. */
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321 | usb_log_debug("Allocating main transfer ring for endpoint " XHCI_EP_FMT,
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322 | XHCI_EP_ARGS(*xhci_ep));
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323 |
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324 | xhci_ep->primary_stream_data_array = NULL;
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325 | xhci_ep->primary_stream_data_size = 0;
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326 |
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327 | errno_t err;
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328 | if ((err = xhci_trb_ring_init(&xhci_ep->ring, 0))) {
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329 | return err;
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330 | }
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331 |
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332 | if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
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333 | if ((err = isoch_alloc_transfers(xhci_ep))) {
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334 | xhci_trb_ring_fini(&xhci_ep->ring);
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335 | return err;
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336 | }
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337 | }
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338 |
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339 | return EOK;
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340 | }
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341 |
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342 | /**
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343 | * Free transfer data structures for XHCI endpoint.
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344 | * @param[in] xhci_ep XHCI endpoint to free data structures for.
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345 | */
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346 | void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *xhci_ep)
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347 | {
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348 | if (xhci_ep->primary_stream_data_size) {
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349 | xhci_stream_free_ds(xhci_ep);
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350 | } else {
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351 | usb_log_debug("Freeing main transfer ring of endpoint " XHCI_EP_FMT,
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352 | XHCI_EP_ARGS(*xhci_ep));
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353 | xhci_trb_ring_fini(&xhci_ep->ring);
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354 | }
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355 |
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356 | if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS)
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357 | isoch_fini(xhci_ep);
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358 | }
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359 |
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360 | xhci_trb_ring_t *xhci_endpoint_get_ring(xhci_endpoint_t *ep, uint32_t stream_id)
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361 | {
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362 | if (ep->primary_stream_data_size == 0)
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363 | return stream_id == 0 ? &ep->ring : NULL;
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364 |
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365 | xhci_stream_data_t *stream_data = xhci_get_stream_ctx_data(ep, stream_id);
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366 | if (stream_data == NULL) {
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367 | usb_log_warning("No transfer ring was found for stream %u.", stream_id);
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368 | return NULL;
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369 | }
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370 |
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371 | return &stream_data->ring;
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372 | }
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373 |
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374 | /**
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375 | * Configure endpoint context of a control endpoint.
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376 | * @param[in] ep XHCI control endpoint.
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377 | * @param[in] ctx Endpoint context to configure.
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378 | */
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379 | static void setup_control_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
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380 | {
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381 | XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
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382 | XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
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383 | XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
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384 | XHCI_EP_MULT_SET(*ctx, ep->mult - 1);
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385 | XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
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386 | XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
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387 | XHCI_EP_DCS_SET(*ctx, 1);
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388 | }
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389 |
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390 | /**
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391 | * Configure endpoint context of a bulk endpoint.
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392 | * @param[in] ep XHCI bulk endpoint.
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393 | * @param[in] ctx Endpoint context to configure.
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394 | */
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395 | static void setup_bulk_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
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396 | {
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397 | XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
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398 | XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
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399 | XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
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400 | XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
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401 |
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402 | XHCI_EP_MAX_P_STREAMS_SET(*ctx, 0);
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403 | XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
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404 | XHCI_EP_DCS_SET(*ctx, 1);
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405 | }
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406 |
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407 | /**
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408 | * Configure endpoint context of a isochronous endpoint.
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409 | * @param[in] ep XHCI isochronous endpoint.
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410 | * @param[in] ctx Endpoint context to configure.
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411 | */
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412 | static void setup_isoch_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
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413 | {
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414 | XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
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415 | XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
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416 | XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
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417 | XHCI_EP_MULT_SET(*ctx, ep->mult - 1);
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418 | XHCI_EP_ERROR_COUNT_SET(*ctx, 0);
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419 | XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
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420 | XHCI_EP_DCS_SET(*ctx, 1);
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421 | XHCI_EP_INTERVAL_SET(*ctx, fnzb32(ep->interval) % 32);
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422 |
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423 | XHCI_EP_MAX_ESIT_PAYLOAD_LO_SET(*ctx, ep->isoch->max_size & 0xFFFF);
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424 | XHCI_EP_MAX_ESIT_PAYLOAD_HI_SET(*ctx, (ep->isoch->max_size >> 16) & 0xFF);
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425 | }
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426 |
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427 | /**
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428 | * Configure endpoint context of a interrupt endpoint.
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429 | * @param[in] ep XHCI interrupt endpoint.
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430 | * @param[in] ctx Endpoint context to configure.
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431 | */
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432 | static void setup_interrupt_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
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433 | {
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434 | XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
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435 | XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
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436 | XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
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437 | XHCI_EP_MULT_SET(*ctx, 0);
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438 | XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
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439 | XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
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440 | XHCI_EP_DCS_SET(*ctx, 1);
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441 | XHCI_EP_INTERVAL_SET(*ctx, fnzb32(ep->interval) % 32);
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442 | // TODO: max ESIT payload
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443 | }
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444 |
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445 | /** Type of endpoint context configuration function. */
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446 | typedef void (*setup_ep_ctx_helper)(xhci_endpoint_t *, xhci_ep_ctx_t *);
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447 |
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448 | /**
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449 | * Static array, which maps USB endpoint types to their respective endpoint
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450 | * context configuration functions.
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451 | */
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452 | static const setup_ep_ctx_helper setup_ep_ctx_helpers[] = {
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453 | [USB_TRANSFER_CONTROL] = setup_control_ep_ctx,
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454 | [USB_TRANSFER_ISOCHRONOUS] = setup_isoch_ep_ctx,
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455 | [USB_TRANSFER_BULK] = setup_bulk_ep_ctx,
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456 | [USB_TRANSFER_INTERRUPT] = setup_interrupt_ep_ctx,
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457 | };
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458 |
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459 | /** Configure endpoint context of XHCI endpoint.
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460 | * @param[in] ep Associated XHCI endpoint.
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461 | * @param[in] ep_ctx Endpoint context to configure.
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462 | */
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463 | void xhci_setup_endpoint_context(xhci_endpoint_t *ep, xhci_ep_ctx_t *ep_ctx)
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464 | {
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465 | assert(ep);
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466 | assert(ep_ctx);
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467 |
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468 | usb_transfer_type_t tt = ep->base.transfer_type;
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469 |
|
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470 | memset(ep_ctx, 0, sizeof(*ep_ctx));
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471 | setup_ep_ctx_helpers[tt](ep, ep_ctx);
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472 | }
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473 |
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474 | /**
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475 | * Clear endpoint halt condition by resetting the endpoint and skipping the
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476 | * offending transfer.
|
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477 | */
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478 | errno_t xhci_endpoint_clear_halt(xhci_endpoint_t *ep, uint32_t stream_id)
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479 | {
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480 | errno_t err;
|
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481 |
|
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482 | if ((err = hc_reset_endpoint(ep)))
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483 | return err;
|
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484 |
|
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485 | if ((err = hc_reset_ring(ep, stream_id)))
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486 | return err;
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487 |
|
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488 | return EOK;
|
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489 | }
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490 |
|
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491 | /**
|
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492 | * @}
|
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493 | */
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