source: mainline/uspace/drv/bus/usb/xhci/endpoint.c

Last change on this file was 09ab0a9a, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix vertical spacing with new Ccheck revision.

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1/*
2 * Copyright (c) 2018 Petr Manek, Ondrej Hlavaty, Michal Staruch, Jan Hrach
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The host controller endpoint management.
34 */
35
36#include <usb/host/endpoint.h>
37#include <usb/descriptor.h>
38
39#include <errno.h>
40#include <macros.h>
41#include <str_error.h>
42
43#include "hc.h"
44#include "bus.h"
45#include "commands.h"
46#include "device.h"
47#include "endpoint.h"
48#include "streams.h"
49
50static errno_t alloc_transfer_ds(xhci_endpoint_t *);
51
52/**
53 * Initialize new XHCI endpoint.
54 * @param[in] xhci_ep Allocated XHCI endpoint to initialize.
55 * @param[in] dev Device, to which the endpoint belongs.
56 * @param[in] desc USB endpoint descriptor carrying configuration data.
57 *
58 * @return Error code.
59 */
60static errno_t xhci_endpoint_init(xhci_endpoint_t *xhci_ep, device_t *dev,
61 const usb_endpoint_descriptors_t *desc)
62{
63 errno_t rc;
64 assert(xhci_ep);
65
66 endpoint_t *ep = &xhci_ep->base;
67
68 endpoint_init(ep, dev, desc);
69
70 fibril_mutex_initialize(&xhci_ep->guard);
71
72 xhci_ep->max_burst = desc->companion.max_burst + 1;
73
74 if (ep->transfer_type == USB_TRANSFER_BULK)
75 xhci_ep->max_streams = 1 << (USB_SSC_MAX_STREAMS(desc->companion));
76 else
77 xhci_ep->max_streams = 1;
78
79 if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS)
80 xhci_ep->mult = USB_SSC_MULT(desc->companion) + 1;
81 else
82 xhci_ep->mult = 1;
83
84 /*
85 * In USB 3, the semantics of wMaxPacketSize changed. Now the number of
86 * packets per service interval is determined from max_burst and mult.
87 */
88 if (dev->speed >= USB_SPEED_SUPER) {
89 ep->packets_per_uframe = xhci_ep->max_burst * xhci_ep->mult;
90 if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS ||
91 ep->transfer_type == USB_TRANSFER_INTERRUPT) {
92 ep->max_transfer_size = ep->max_packet_size * ep->packets_per_uframe;
93 }
94 }
95
96 xhci_ep->interval = desc->endpoint.poll_interval;
97
98 /*
99 * Only Low/Full speed interrupt endpoints have interval as a linear field,
100 * others have 2-based log of it.
101 */
102 if (dev->speed >= USB_SPEED_HIGH ||
103 ep->transfer_type != USB_TRANSFER_INTERRUPT) {
104
105 // XXX: According to the spec, the interval should be
106 // from [1, 16]. However, in QEMU, we get 0 here
107 // (a QEMU bug?).
108 if (xhci_ep->interval == 0)
109 xhci_ep->interval = 8;
110
111 xhci_ep->interval = 1 << (xhci_ep->interval - 1);
112 }
113
114 /* Full speed devices have interval in frames */
115 if (dev->speed <= USB_SPEED_FULL) {
116 xhci_ep->interval *= 8;
117 }
118
119 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS)
120 isoch_init(xhci_ep, desc);
121
122 if ((rc = alloc_transfer_ds(xhci_ep)))
123 goto err;
124
125 unsigned flags = -1U;
126
127 /* Some xHCs can handle 64-bit addresses */
128 xhci_bus_t *bus = bus_to_xhci_bus(ep->device->bus);
129 if (bus->hc->ac64)
130 flags &= ~DMA_POLICY_4GiB;
131
132 /* xHCI works best if it can fit 65k transfers in one TRB */
133 ep->transfer_buffer_policy = dma_policy_create(flags, 1 << 16);
134
135 /* But actualy can do full scatter-gather. */
136 ep->required_transfer_buffer_policy = dma_policy_create(flags, PAGE_SIZE);
137
138 return EOK;
139
140err:
141 return rc;
142}
143
144/**
145 * Create a new xHCI endpoint structure.
146 *
147 * Bus callback.
148 */
149endpoint_t *xhci_endpoint_create(device_t *dev,
150 const usb_endpoint_descriptors_t *desc)
151{
152 const usb_transfer_type_t type = USB_ED_GET_TRANSFER_TYPE(desc->endpoint);
153
154 xhci_endpoint_t *ep = calloc(1, sizeof(xhci_endpoint_t) +
155 (type == USB_TRANSFER_ISOCHRONOUS) * sizeof(*ep->isoch));
156 if (!ep)
157 return NULL;
158
159 if (xhci_endpoint_init(ep, dev, desc)) {
160 free(ep);
161 return NULL;
162 }
163
164 return &ep->base;
165}
166
167/**
168 * Finalize XHCI endpoint.
169 * @param[in] xhci_ep XHCI endpoint to finalize.
170 */
171static void xhci_endpoint_fini(xhci_endpoint_t *xhci_ep)
172{
173 assert(xhci_ep);
174
175 xhci_endpoint_free_transfer_ds(xhci_ep);
176
177 // TODO: Something missed?
178}
179
180/**
181 * Destroy given xHCI endpoint structure.
182 *
183 * Bus callback.
184 */
185void xhci_endpoint_destroy(endpoint_t *ep)
186{
187 xhci_endpoint_t *xhci_ep = xhci_endpoint_get(ep);
188
189 xhci_endpoint_fini(xhci_ep);
190 free(xhci_ep);
191}
192
193/**
194 * Register an andpoint to the xHC.
195 *
196 * Bus callback.
197 */
198errno_t xhci_endpoint_register(endpoint_t *ep_base)
199{
200 errno_t err;
201 xhci_endpoint_t *ep = xhci_endpoint_get(ep_base);
202
203 if (ep_base->endpoint != 0 && (err = hc_add_endpoint(ep)))
204 return err;
205
206 endpoint_set_online(ep_base, &ep->guard);
207 return EOK;
208}
209
210/**
211 * Abort a transfer on an endpoint.
212 */
213static void endpoint_abort(endpoint_t *ep)
214{
215 xhci_device_t *dev = xhci_device_get(ep->device);
216 xhci_endpoint_t *xhci_ep = xhci_endpoint_get(ep);
217
218 /* This function can only abort endpoints without streams. */
219 assert(xhci_ep->primary_stream_data_array == NULL);
220
221 fibril_mutex_lock(&xhci_ep->guard);
222
223 endpoint_set_offline_locked(ep);
224
225 if (!ep->active_batch) {
226 fibril_mutex_unlock(&xhci_ep->guard);
227 return;
228 }
229
230 /* First, offer the batch a short chance to be finished. */
231 endpoint_wait_timeout_locked(ep, 10000);
232
233 if (!ep->active_batch) {
234 fibril_mutex_unlock(&xhci_ep->guard);
235 return;
236 }
237
238 usb_transfer_batch_t *const batch = ep->active_batch;
239
240 const errno_t err = hc_stop_endpoint(xhci_ep);
241 if (err) {
242 usb_log_error("Failed to stop endpoint %u of device "
243 XHCI_DEV_FMT ": %s", ep->endpoint, XHCI_DEV_ARGS(*dev),
244 str_error(err));
245 }
246
247 fibril_mutex_unlock(&xhci_ep->guard);
248
249 batch->error = EINTR;
250 batch->transferred_size = 0;
251 usb_transfer_batch_finish(batch);
252 return;
253}
254
255/**
256 * Unregister an endpoint. If the device is still available, inform the xHC
257 * about it.
258 *
259 * Bus callback.
260 */
261void xhci_endpoint_unregister(endpoint_t *ep_base)
262{
263 errno_t err;
264 xhci_endpoint_t *ep = xhci_endpoint_get(ep_base);
265 xhci_device_t *dev = xhci_device_get(ep_base->device);
266
267 endpoint_abort(ep_base);
268
269 /* If device slot is still available, drop the endpoint. */
270 if (ep_base->endpoint != 0 && dev->slot_id) {
271
272 if ((err = hc_drop_endpoint(ep))) {
273 usb_log_error("Failed to drop endpoint " XHCI_EP_FMT ": %s",
274 XHCI_EP_ARGS(*ep), str_error(err));
275 }
276 } else {
277 usb_log_debug("Not going to drop endpoint " XHCI_EP_FMT " because"
278 " the slot has already been disabled.", XHCI_EP_ARGS(*ep));
279 }
280}
281
282/**
283 * Determine the type of a XHCI endpoint.
284 * @param[in] ep XHCI endpoint to query.
285 *
286 * @return EP_TYPE_[CONTROL|ISOCH|BULK|INTERRUPT]_[IN|OUT]
287 */
288int xhci_endpoint_type(xhci_endpoint_t *ep)
289{
290 const bool in = ep->base.direction == USB_DIRECTION_IN;
291
292 switch (ep->base.transfer_type) {
293 case USB_TRANSFER_CONTROL:
294 return EP_TYPE_CONTROL;
295
296 case USB_TRANSFER_ISOCHRONOUS:
297 return in ? EP_TYPE_ISOCH_IN :
298 EP_TYPE_ISOCH_OUT;
299
300 case USB_TRANSFER_BULK:
301 return in ? EP_TYPE_BULK_IN :
302 EP_TYPE_BULK_OUT;
303
304 case USB_TRANSFER_INTERRUPT:
305 return in ? EP_TYPE_INTERRUPT_IN :
306 EP_TYPE_INTERRUPT_OUT;
307 }
308
309 return EP_TYPE_INVALID;
310}
311
312/**
313 * Allocate transfer data structures for XHCI endpoint not using streams.
314 * @param[in] xhci_ep XHCI endpoint to allocate data structures for.
315 *
316 * @return Error code.
317 */
318static errno_t alloc_transfer_ds(xhci_endpoint_t *xhci_ep)
319{
320 /* Can't use XHCI_EP_FMT because the endpoint may not have device. */
321 usb_log_debug("Allocating main transfer ring for endpoint " XHCI_EP_FMT,
322 XHCI_EP_ARGS(*xhci_ep));
323
324 xhci_ep->primary_stream_data_array = NULL;
325 xhci_ep->primary_stream_data_size = 0;
326
327 errno_t err;
328 if ((err = xhci_trb_ring_init(&xhci_ep->ring, 0))) {
329 return err;
330 }
331
332 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
333 if ((err = isoch_alloc_transfers(xhci_ep))) {
334 xhci_trb_ring_fini(&xhci_ep->ring);
335 return err;
336 }
337 }
338
339 return EOK;
340}
341
342/**
343 * Free transfer data structures for XHCI endpoint.
344 * @param[in] xhci_ep XHCI endpoint to free data structures for.
345 */
346void xhci_endpoint_free_transfer_ds(xhci_endpoint_t *xhci_ep)
347{
348 if (xhci_ep->primary_stream_data_size) {
349 xhci_stream_free_ds(xhci_ep);
350 } else {
351 usb_log_debug("Freeing main transfer ring of endpoint " XHCI_EP_FMT,
352 XHCI_EP_ARGS(*xhci_ep));
353 xhci_trb_ring_fini(&xhci_ep->ring);
354 }
355
356 if (xhci_ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS)
357 isoch_fini(xhci_ep);
358}
359
360xhci_trb_ring_t *xhci_endpoint_get_ring(xhci_endpoint_t *ep, uint32_t stream_id)
361{
362 if (ep->primary_stream_data_size == 0)
363 return stream_id == 0 ? &ep->ring : NULL;
364
365 xhci_stream_data_t *stream_data = xhci_get_stream_ctx_data(ep, stream_id);
366 if (stream_data == NULL) {
367 usb_log_warning("No transfer ring was found for stream %u.", stream_id);
368 return NULL;
369 }
370
371 return &stream_data->ring;
372}
373
374/**
375 * Configure endpoint context of a control endpoint.
376 * @param[in] ep XHCI control endpoint.
377 * @param[in] ctx Endpoint context to configure.
378 */
379static void setup_control_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
380{
381 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
382 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
383 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
384 XHCI_EP_MULT_SET(*ctx, ep->mult - 1);
385 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
386 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
387 XHCI_EP_DCS_SET(*ctx, 1);
388}
389
390/**
391 * Configure endpoint context of a bulk endpoint.
392 * @param[in] ep XHCI bulk endpoint.
393 * @param[in] ctx Endpoint context to configure.
394 */
395static void setup_bulk_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
396{
397 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
398 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size);
399 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
400 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
401
402 XHCI_EP_MAX_P_STREAMS_SET(*ctx, 0);
403 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
404 XHCI_EP_DCS_SET(*ctx, 1);
405}
406
407/**
408 * Configure endpoint context of a isochronous endpoint.
409 * @param[in] ep XHCI isochronous endpoint.
410 * @param[in] ctx Endpoint context to configure.
411 */
412static void setup_isoch_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
413{
414 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
415 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
416 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
417 XHCI_EP_MULT_SET(*ctx, ep->mult - 1);
418 XHCI_EP_ERROR_COUNT_SET(*ctx, 0);
419 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
420 XHCI_EP_DCS_SET(*ctx, 1);
421 XHCI_EP_INTERVAL_SET(*ctx, fnzb32(ep->interval) % 32);
422
423 XHCI_EP_MAX_ESIT_PAYLOAD_LO_SET(*ctx, ep->isoch->max_size & 0xFFFF);
424 XHCI_EP_MAX_ESIT_PAYLOAD_HI_SET(*ctx, (ep->isoch->max_size >> 16) & 0xFF);
425}
426
427/**
428 * Configure endpoint context of a interrupt endpoint.
429 * @param[in] ep XHCI interrupt endpoint.
430 * @param[in] ctx Endpoint context to configure.
431 */
432static void setup_interrupt_ep_ctx(xhci_endpoint_t *ep, xhci_ep_ctx_t *ctx)
433{
434 XHCI_EP_TYPE_SET(*ctx, xhci_endpoint_type(ep));
435 XHCI_EP_MAX_PACKET_SIZE_SET(*ctx, ep->base.max_packet_size & 0x07FF);
436 XHCI_EP_MAX_BURST_SIZE_SET(*ctx, ep->max_burst - 1);
437 XHCI_EP_MULT_SET(*ctx, 0);
438 XHCI_EP_ERROR_COUNT_SET(*ctx, 3);
439 XHCI_EP_TR_DPTR_SET(*ctx, ep->ring.dequeue);
440 XHCI_EP_DCS_SET(*ctx, 1);
441 XHCI_EP_INTERVAL_SET(*ctx, fnzb32(ep->interval) % 32);
442 // TODO: max ESIT payload
443}
444
445/** Type of endpoint context configuration function. */
446typedef void (*setup_ep_ctx_helper)(xhci_endpoint_t *, xhci_ep_ctx_t *);
447
448/**
449 * Static array, which maps USB endpoint types to their respective endpoint
450 * context configuration functions.
451 */
452static const setup_ep_ctx_helper setup_ep_ctx_helpers[] = {
453 [USB_TRANSFER_CONTROL] = setup_control_ep_ctx,
454 [USB_TRANSFER_ISOCHRONOUS] = setup_isoch_ep_ctx,
455 [USB_TRANSFER_BULK] = setup_bulk_ep_ctx,
456 [USB_TRANSFER_INTERRUPT] = setup_interrupt_ep_ctx,
457};
458
459/** Configure endpoint context of XHCI endpoint.
460 * @param[in] ep Associated XHCI endpoint.
461 * @param[in] ep_ctx Endpoint context to configure.
462 */
463void xhci_setup_endpoint_context(xhci_endpoint_t *ep, xhci_ep_ctx_t *ep_ctx)
464{
465 assert(ep);
466 assert(ep_ctx);
467
468 usb_transfer_type_t tt = ep->base.transfer_type;
469
470 memset(ep_ctx, 0, sizeof(*ep_ctx));
471 setup_ep_ctx_helpers[tt](ep, ep_ctx);
472}
473
474/**
475 * Clear endpoint halt condition by resetting the endpoint and skipping the
476 * offending transfer.
477 */
478errno_t xhci_endpoint_clear_halt(xhci_endpoint_t *ep, uint32_t stream_id)
479{
480 errno_t err;
481
482 if ((err = hc_reset_endpoint(ep)))
483 return err;
484
485 if ((err = hc_reset_ring(ep, stream_id)))
486 return err;
487
488 return EOK;
489}
490
491/**
492 * @}
493 */
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