Changeset d70ebffe in mainline for kernel/arch/sparc64/src/mm/sun4u/tlb.c

Timestamp:

2014-10-27T15:10:14Z (10 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

aef669b

Parents:

ec443d5

Message:

Let the fast MMU traps use exc_dispatch() in their slow-path.

In order to get proper exception accounting, the MMU related traps need
to go through the code in exc_dispatch(). To make this possible, we pass
the DTLB Tag Access register in istate_t in order to make way for the
trap type argument, which needs to be passed as the first argument to
exc_dispatch().

As a collateral change, this commit modifies the istate_t structure to
match the SPARC V9 ABI stack frame layout. It gives us a richer istate_t
with more information in it and also simplifies calculation of stack
offsets inside of preemptible_handler.

File:

• kernel/arch/sparc64/src/mm/sun4u/tlb.c (modified) (5 diffs)

kernel/arch/sparc64/src/mm/sun4u/tlb.c

@@ -194 +194 @@
 
 /** ITLB miss handler. */
-void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
+void fast_instruction_access_mmu_miss(unsigned int tt, istate_t *istate)
 {
         size_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
@@ -224 +224 @@
  * low-level, assembly language part of the fast_data_access_mmu_miss handler.
  *
- * @param tag           Content of the TLB Tag Access register as it existed
- *                      when the trap happened. This is to prevent confusion
- *                      created by clobbered Tag Access register during a nested
- *                      DTLB miss.
+ * @param tt            Trap type.
  * @param istate        Interrupted state saved on the stack.
  */
-void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
-{
+void fast_data_access_mmu_miss(unsigned int tt, istate_t *istate)
+{
+        tlb_tag_access_reg_t tag;
         uintptr_t page_8k;
         uintptr_t page_16k;
@@ -238 +236 @@
         as_t *as = AS;
 
+        tag.value = istate->tlb_tag_access;
         page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH;
         page_16k = ALIGN_DOWN(page_8k, PAGE_SIZE);
@@ -276 +275 @@
 /** DTLB protection fault handler.
  *
- * @param tag           Content of the TLB Tag Access register as it existed
- *                      when the trap happened. This is to prevent confusion
- *                      created by clobbered Tag Access register during a nested
- *                      DTLB miss.
+ * @param tt            Trap type.
  * @param istate        Interrupted state saved on the stack.
  */
-void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
-{
+void fast_data_access_protection(unsigned int tt, istate_t *istate)
+{
+        tlb_tag_access_reg_t tag;
         uintptr_t page_16k;
         size_t index;
@@ -289 +286 @@
         as_t *as = AS;
 
+        tag.value = istate->tlb_tag_access;
         page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
         index = tag.vpn % MMU_PAGES_PER_PAGE;   /* 16K-page emulation */