Changeset d70ebffe in mainline for kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h

Timestamp:

2014-10-27T15:10:14Z (10 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

aef669b

Parents:

ec443d5

Message:

Let the fast MMU traps use exc_dispatch() in their slow-path.

In order to get proper exception accounting, the MMU related traps need
to go through the code in exc_dispatch(). To make this possible, we pass
the DTLB Tag Access register in istate_t in order to make way for the
trap type argument, which needs to be passed as the first argument to
exc_dispatch().

As a collateral change, this commit modifies the istate_t structure to
match the SPARC V9 ABI stack frame layout. It gives us a richer istate_t
with more information in it and also simplifies calculation of stack
offsets inside of preemptible_handler.

File:

• kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h (modified) (4 diffs)

kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h

@@ -74 +74 @@
 0:
         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
-        PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
+        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
+        mov VA_IMMU_TAG_ACCESS, %g5
+        ldxa [%g5] ASI_IMMU, %g5                        ! read the faulting Context and VPN
+        PREEMPTIBLE_HANDLER exc_dispatch 
 .endm
 
@@ -107 +110 @@
         wr %g0, ASI_DMMU, %asi
         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1             ! read the faulting Context and VPN
-        set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
+        ldx [%g7 + %lo(tlb_tag_access_context_mask)], %g2
         andcc %g1, %g2, %g3                             ! get Context
         bnz %xcc, 0f                                    ! Context is non-zero
@@ -138 +141 @@
         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
 
-        /*
-         * Read the Tag Access register for the higher-level handler.
-         * This is necessary to survive nested DTLB misses.
-         */     
-        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2
-
-        /*
-         * g2 will be passed as an argument to fast_data_access_mmu_miss().
-         */
-        PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
+        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
+        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g5             ! read the faulting Context and VPN
+        PREEMPTIBLE_HANDLER exc_dispatch 
 .endm
 
@@ -164 +160 @@
         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
 
-        /*
-         * Read the Tag Access register for the higher-level handler.
-         * This is necessary to survive nested DTLB misses.
-         */     
-        mov VA_DMMU_TAG_ACCESS, %g2
-        ldxa [%g2] ASI_DMMU, %g2
-
-        /*
-         * g2 will be passed as an argument to fast_data_access_mmu_miss().
-         */
-        PREEMPTIBLE_HANDLER fast_data_access_protection
+        mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
+        mov VA_DMMU_TAG_ACCESS, %g5
+        ldxa [%g5] ASI_DMMU, %g5                        ! read the faulting Context and VPN
+        PREEMPTIBLE_HANDLER exc_dispatch 
 .endm