Changeset cc74cb5 in mainline for kernel/arch/ia64/src/fpu_context.c

Timestamp:

2018-09-14T23:15:04Z (7 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6f58770

Parents:

09ab0a9a

Message:

Set FPSR.sf1 controls to standard values

The Itanium Software Conventions and Runtime Architecture Guide reserves
the Status Field 1 of FPSR to be used by the divide and square root code
and requires that it has certain standard values.

File:

• kernel/arch/ia64/src/fpu_context.c (modified) (1 diff)

kernel/arch/ia64/src/fpu_context.c

@@ -491 +491 @@
             "mov ar.fpsr = %0 ;;\n"
             : "+r" (a)
-            : "r" (FPSR_TRAPS_ALL)
+            : "r" (FPSR_TRAPS_ALL | FPSR_SF1_CTRL)
         );