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Changeset cc74cb5 in mainline


Ignore:
Timestamp:
2018-09-14T23:15:04Z (3 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master
Children:
6f58770
Parents:
09ab0a9a
Message:

Set FPSR.sf1 controls to standard values

The Itanium Software Conventions and Runtime Architecture Guide reserves
the Status Field 1 of FPSR to be used by the divide and square root code
and requires that it has certain standard values.

Location:
kernel/arch/ia64
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia64/include/arch/context.h

    r09ab0a9a rcc74cb5  
    5757                (c)->bsp = ((uintptr_t) stack) + ALIGN_UP((size / 2), REGISTER_STACK_ALIGNMENT); \
    5858                (c)->ar_pfs &= PFM_MASK; \
    59                 (c)->ar_fpsr = FPSR_TRAPS_ALL; \
     59                (c)->ar_fpsr = FPSR_TRAPS_ALL | FPSR_SF1_CTRL; \
    6060                (c)->sp = ((uintptr_t) stack) + ALIGN_UP((size / 2), STACK_ALIGNMENT) - SP_DELTA; \
    6161                (c)->r1 = (uintptr_t) &__gp; \
  • kernel/arch/ia64/include/arch/register.h

    r09ab0a9a rcc74cb5  
    7878#define FPSR_TRAPS_ALL (FPSR_TRAPS_VD | FPSR_TRAPS_DD | FPSR_TRAPS_ZD | \
    7979    FPSR_TRAPS_OD | FPSR_TRAPS_UD | FPSR_TRAPS_ID)
     80
     81#define FPSR_SF1_SHIFT 19
     82
     83#define FPSR_CTRL_WRE           (1 << 1)
     84#define FPSR_CTRL_PC_EXTENDED   (3 << 2)
     85#define FPSR_CTRL_RC_NEAREST    (0 << 4)
     86#define FPSR_CTRL_TD            (1 << 6)
     87
     88#define FPSR_SF1_CTRL ((FPSR_CTRL_WRE | FPSR_CTRL_PC_EXTENDED | \
     89    FPSR_CTRL_RC_NEAREST | FPSR_CTRL_TD) << FPSR_SF1_SHIFT)
    8090
    8191/** Application registers. */
  • kernel/arch/ia64/src/fpu_context.c

    r09ab0a9a rcc74cb5  
    491491            "mov ar.fpsr = %0 ;;\n"
    492492            : "+r" (a)
    493             : "r" (FPSR_TRAPS_ALL)
     493            : "r" (FPSR_TRAPS_ALL | FPSR_SF1_CTRL)
    494494        );
    495495
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