Changeset b97b348 in mainline for kernel/arch/sparc64/include/mm/cache_spec.h

Timestamp:

2010-05-12T20:00:19Z (14 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

be6cef1b

Parents:

f09d891

Message:

do not use ofw_quiesce() (it can actually make more harm than good)
fix the order of arguments passed from the bootloader to kernel on sparc64 (this fixes booting on machines with non-zero physical address start)
remove separate cache.S, use the code directly in start.S

File:

• kernel/arch/sparc64/include/mm/cache_spec.h (modified) (2 diffs)

kernel/arch/sparc64/include/mm/cache_spec.h

@@ -27 +27 @@
  */
 
-/** @addtogroup sparc64mm       
+/** @addtogroup sparc64mm
  * @{
  */
@@ -39 +39 @@
  * The following macros are valid for the following processors:
  *
- *      UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
- *      UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
- * 
+ *  UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
+ *  UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
+ *
  * Should we support other UltraSPARC processors, we need to make sure that
  * the macros are defined correctly for them.
  */
- 
+
 #if defined (US)
-#define DCACHE_SIZE             (16 * 1024)
+        #define DCACHE_SIZE  (16 * 1024)
 #elif defined (US3)
-#define DCACHE_SIZE             (64 * 1024)
+        #define DCACHE_SIZE  (64 * 1024)
 #endif
-#define DCACHE_LINE_SIZE        32      
+
+#define DCACHE_LINE_SIZE  32
+#define DCACHE_TAG_SHIFT  2
 
 #endif