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Changeset b80d132 in mainline


Ignore:
Timestamp:
2013-01-23T20:48:23Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
df334ca
Parents:
bfb6576
Message:

arm32, boot: Flush everything to PoC (memory) and disable caches before reaching kernel

This should be safe for all ARMs. Kernel will enable caches if it is supported.

Location:
boot/arch/arm32/src
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/src/asm.S

    rbfb6576 rb80d132  
    6666        # r2 is a kernel text end
    6767
     68#define CP15_C1_IC              12
     69#define CP15_C1_BP              11
     70#define CP15_C1_DC              2
     71        # Disable I-cache and D-cache before the kernel is started.
     72        mrc     p15, 0, r4, c1, c0, 0
     73        bic     r4, r4, #(1 << CP15_C1_DC)
     74        bic     r4, r4, #(1 << CP15_C1_IC)
     75        bic     r4, r4, #(1 << CP15_C1_BP)
     76        mcr     p15, 0, r4, c1, c0, 0
     77
    6878       
    6979        #Wait for the operations to complete
     
    8999#endif
    90100       
     101#TODO:This should not be necessary
    91102
    92103#if defined(MACHINE_gta02)
    93104
    94 #define CP15_C1_IC              12
    95 #define CP15_C1_DC              2
    96105#define CP15_C7_SEG_SHIFT       5
    97106#define CP15_C7_SEG_SIZE        3
    98107#define CP15_C7_IDX_SHIFT       26
    99 
    100         # Disable I-cache and D-cache before the kernel is started.
    101         mrc     p15, 0, r4, c1, c0, 0
    102         bic     r4, r4, #(1 << CP15_C1_DC)
    103         bic     r4, r4, #(1 << CP15_C1_IC)
    104         mcr     p15, 0, r4, c1, c0, 0
    105108
    106109        # Now clean D-cache to guarantee coherency between I-cache and D-cache.
  • boot/arch/arm32/src/main.c

    rbfb6576 rb80d132  
    6969}
    7070
    71 static inline void clean_dcache_pou(void *address, size_t size)
     71static inline void clean_dcache_poc(void *address, size_t size)
    7272{
    7373        const uintptr_t addr = (uintptr_t)address;
    74         /* DCCMVAU - clean by address to the point of unification */
     74        /* DCCMVAC - clean by address to the point of coherence */
    7575        for (uintptr_t a = addr; a < addr + size; a += 4) {
    76                 asm volatile ("mcr p15, 0, %[a], c7, c11, 1\n" :: [a]"r"(a) : );
     76                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
    7777        }
    7878}
     
    148148                        halt();
    149149                }
    150                 clean_dcache_pou(dest[i - 1], components[i - 1].inflated);
     150                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
    151151        }
    152152       
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