Changeset df334ca in mainline


Ignore:
Timestamp:
2013-01-23T20:52:46Z (11 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
cfeb368
Parents:
b80d132
Message:

arm32, boot: Enable all caches on all ARMs.

We disable them again later.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • boot/arch/arm32/src/mm.c

    rb80d132 rdf334ca  
    136136                "mrc p15, 0, r0, c1, c0, 0\n"
    137137               
    138 #if defined(PROCESSOR_cortex_a8) | defined(MACHINE_gta02)
    139                 /* Mask to enable paging, I-cache D-cache and branch predict
    140                  * See kernel/arch/arm32/include/regutils.h for bit values.
    141                  * It's safe because Cortex-A8 implements IVIPT extension
    142                  * See Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245).
    143                  * It's safe for gta02 too because we turn the caches off
    144                  * before switching to kernel. */
    145                 "ldr r1, =0x00001801\n"
    146 #elif defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
    147                 /* Enable paging, data cache and branch prediction
    148                  * see arch/arm32/src/cpu/cpu.c for reasoning */
    149                 "ldr r1, =0x00000805\n"
    150 #else
    151                 /* Mask to enable paging */
    152                 "ldr r1, =0x00000001\n"
    153 #endif
     138                /* Enable ICache, DCache, BPredictors and MMU,
     139                 * we disable caches before jumping to kernel
     140                 * so this is safe for all archs.
     141                 */
     142                "ldr r1, =0x00001805\n"
     143               
    154144                "orr r0, r0, r1\n"
    155145               
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