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Changeset bfb6576 in mainline


Ignore:
Timestamp:
2013-01-23T00:12:15Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
b80d132
Parents:
c19808fd
Message:

arm32, boot: Rework boot time cache handling. Enable Icache early.

Dcache still hangs after jumping to kernel.

Location:
boot/arch/arm32
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/_link.ld.in

    rc19808fd rbfb6576  
    1111        . = BOOT_BASE + 0x8000;
    1212        .data : {
     13                bdata_start = .;
    1314                *(BOOTPT);      /* bootstrap page table */
    1415                *(BOOTSTACK);   /* bootstrap stack */
     
    2425[[COMPONENTS]]
    2526        }
    26        
     27        bdata_end = .;
     28
    2729        /DISCARD/ : {
    2830                *(.gnu.*);
  • boot/arch/arm32/src/asm.S

    rc19808fd rbfb6576  
    6666        # r2 is a kernel text end
    6767
    68         # make sure kernel is flushed and available in memory
    69         # Disable I-cache and D-cache before the kernel is started.
    70         # TODO disabling DCache should not be necessary...
    71 #define CP15_C1_IC              12
    72 #define CP15_C1_DC              2
    73         mrc     p15, 0, r4, c1, c0, 0
    74         bic     r4, r4, #(1 << CP15_C1_DC)
    75         bic     r4, r4, #(1 << CP15_C1_IC)
    76         mcr     p15, 0, r4, c1, c0, 0
    77 
    78         # use r4 as a moving pointer
    79         mov r4, r0
    80 3:
    81         # DCCMVAC (flush by virt address, to the point of coherence)
    82         mcr p15, 0, r4, c7, c10, 1
    83         # TODO: it would be better to use cacheline size
    84         add r4, r4, #4
    85         # are we there yet?
    86         cmp r4, r2
    87         blt 3b
    88         nop
    89         mov r4, #0
    9068       
    9169        #Wait for the operations to complete
     
    9977        # Clean ICache and BPredictors, r4 ignored (SBZ)
    10078        mcr p15, 0, r4, c7, c5, 0
     79        nop
    10180
    10281        #Wait for the operations to complete
    10382#ifdef PROCESSOR_ARCH_armv7_a
    10483        isb
     84        nop
    10585#else
    10686        # cp15 isb
    10787        mcr p15, 0, r4, c7, c5, 4
     88        nop
    10889#endif
    10990       
  • boot/arch/arm32/src/main.c

    rc19808fd rbfb6576  
    5050#define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
    5151
     52extern void *bdata_start;
     53extern void *bdata_end;
     54
     55
     56static inline void invalidate_icache(void)
     57{
     58        /* ICIALLU Invalidate entire ICache */
     59        asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
     60}
     61
     62static inline void invalidate_dcache(void *address, size_t size)
     63{
     64        const uintptr_t addr = (uintptr_t)address;
     65        /* DCIMVAC - invalidate by address to the point of coherence */
     66        for (uintptr_t a = addr; a < addr + size; a += 4) {
     67                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
     68        }
     69}
     70
     71static inline void clean_dcache_pou(void *address, size_t size)
     72{
     73        const uintptr_t addr = (uintptr_t)address;
     74        /* DCCMVAU - clean by address to the point of unification */
     75        for (uintptr_t a = addr; a < addr + size; a += 4) {
     76                asm volatile ("mcr p15, 0, %[a], c7, c11, 1\n" :: [a]"r"(a) : );
     77        }
     78}
     79
    5280static bootinfo_t bootinfo;
    5381
    5482void bootstrap(void)
    5583{
     84        /* Make sure  we run in memory code when caches are enabled,
     85         * make sure we read memory data too. This part is ARMv7 specific as
     86         * ARMv7 no longer invalidates caches on restart.
     87         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
     88        invalidate_icache();
     89        invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
     90
     91        /* Enable MMU and caches */
    5692        mmu_start();
    5793        version_print();
    5894       
     95        printf("Boot data: %p -> %p\n", &bdata_start, &bdata_end);
    5996        printf("\nMemory statistics\n");
    6097        printf(" %p|%p: bootstrap stack\n", &boot_stack, &boot_stack);
     
    64101            (void *) PA2KA(BOOT_OFFSET), (void *) BOOT_OFFSET);
    65102       
    66         size_t i;
    67         for (i = 0; i < COMPONENTS; i++)
     103        for (size_t i = 0; i < COMPONENTS; i++) {
    68104                printf(" %p|%p: %s image (%u/%u bytes)\n", components[i].start,
    69105                    components[i].start, components[i].name, components[i].inflated,
    70106                    components[i].size);
     107                invalidate_dcache(components[i].start, components[i].size);
     108        }
    71109       
    72110        void *dest[COMPONENTS];
     
    74112        size_t cnt = 0;
    75113        bootinfo.cnt = 0;
    76         for (i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
     114        for (size_t i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
    77115                top = ALIGN_UP(top, PAGE_SIZE);
    78116               
     
    94132        printf("\nInflating components ... ");
    95133       
    96         for (i = cnt; i > 0; i--) {
     134        for (size_t i = cnt; i > 0; i--) {
    97135                void *tail = components[i - 1].start + components[i - 1].size;
    98136                if (tail >= dest[i - 1]) {
     
    106144                int err = inflate(components[i - 1].start, components[i - 1].size,
    107145                    dest[i - 1], components[i - 1].inflated);
    108                
    109146                if (err != EOK) {
    110147                        printf("\n%s: Inflating error %d\n", components[i - 1].name, err);
    111148                        halt();
    112149                }
     150                clean_dcache_pou(dest[i - 1], components[i - 1].inflated);
    113151        }
    114152       
  • boot/arch/arm32/src/mm.c

    rc19808fd rbfb6576  
    5959        const unsigned long address = section << PTE_SECTION_SHIFT;
    6060        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
    61                 return 0;
     61                return 1;
    6262#endif
    6363        return 0;
     
    133133                "mcr p15, 0, r0, c3, c0, 0\n"
    134134               
    135 #ifdef PROCESSOR_ARCH_armv7_a
    136                 /* armv7 no longer requires cache entries to be invalid
    137                  * upon reset, do this manually */
    138                 /* Invalidate ICache */
    139                 "mcr p15, 0, r0, c7, c5, 6\n"
    140                 //TODO: Invalidate data cache
    141 #endif
    142 
    143135                /* Current settings */
    144136                "mrc p15, 0, r0, c1, c0, 0\n"
     
    151143                 * It's safe for gta02 too because we turn the caches off
    152144                 * before switching to kernel. */
    153                 "ldr r1, =0x00001805\n"
     145                "ldr r1, =0x00001801\n"
    154146#elif defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
    155147                /* Enable paging, data cache and branch prediction
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