Changeset 7bdcc45 in mainline for kernel/arch/ia32/src/smp/apic.c
- Timestamp:
- 2010-12-16T16:38:49Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 7837101
- Parents:
- 8e58f94 (diff), eb221e5 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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kernel/arch/ia32/src/smp/apic.c
r8e58f94 r7bdcc45 72 72 * 73 73 */ 74 volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;75 volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;74 volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000); 75 volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000); 76 76 77 77 uint32_t apic_id_mask = 0; … … 184 184 * Other interrupts will be forwarded to the lowest priority CPU. 185 185 */ 186 io_apic_disable_irqs(0xffff );186 io_apic_disable_irqs(0xffffU); 187 187 188 188 irq_initialize(&l_apic_timer_irq); … … 477 477 { 478 478 #ifdef LAPIC_VERBOSE 479 printf("LVT on cpu% " PRIs ", LAPIC ID: %" PRIu8 "\n",479 printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n", 480 480 CPU->id, l_apic_id()); 481 481
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