Changeset 67d02bb in mainline for boot/arch/arm32/src/main.c


Ignore:
Timestamp:
2013-08-03T22:31:18Z (11 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
186b919
Parents:
296a80e
Message:

rm32, boot: Clear entire Dcache on startup.

Specs require this.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/src/main.c

    r296a80e r67d02bb  
    5353extern void *bdata_end;
    5454
    55 
    56 static inline void invalidate_icache(void)
    57 {
    58         /* ICIALLU Invalidate entire ICache */
    59         asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
    60 }
    61 
    62 static inline void invalidate_dcache(void *address, size_t size)
    63 {
    64         const uintptr_t addr = (uintptr_t)address;
    65         for (uintptr_t a = addr; a < addr + size; a += 4) {
    66                 /* DCIMVAC - invalidate by address to the point of coherence */
    67                 asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
    68         }
    69 }
    70 
    7155static inline void clean_dcache_poc(void *address, size_t size)
    7256{
     
    8266void bootstrap(void)
    8367{
    84         /* Make sure we run in memory code when caches are enabled,
    85          * make sure we read memory data too. This part is ARMv7 specific as
    86          * ARMv7 no longer invalidates caches on restart.
    87          * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
    88         invalidate_icache();
    89         invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
    90 
    9168        /* Enable MMU and caches */
    9269        mmu_start();
     
    10582                    components[i].start, components[i].name, components[i].inflated,
    10683                    components[i].size);
    107                 /* Make sure there is no cache garbage in read locations */
    108                 invalidate_dcache(components[i].start, components[i].size);
    10984        }
    11085       
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