Changeset 296a80e in mainline

Timestamp:

2013-08-03T22:16:12Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

67d02bb

Parents:

9120b69

Message:

arm32: Fix pt mapping, and enable caches in early boot.

Files:

• boot/arch/arm32/src/asm.S (modified) (3 diffs)
• kernel/arch/arm32/include/arch/mm/page_armv6.h (modified) (5 diffs)

boot/arch/arm32/src/asm.S

@@ -56 +56 @@
 jump_to_kernel:
         #
-        # TODO
         # Make sure that the I-cache, D-cache and memory are mutually coherent
         # before passing control to the copied code.
@@ -68 +67 @@
 #define CP15_C1_BP              11
 #define CP15_C1_DC              2
-        # Disable I-cache and D-cache before the kernel is started.
+
+
+#ifndef PROCESSOR_ARCH_armv7_a
         mrc     p15, 0, r4, c1, c0, 0
+        
+        # D-cache before the kernel is started.
         bic     r4, r4, #(1 << CP15_C1_DC)
-#ifndef PROCESSOR_ARCH_armv7_a
+
+        #Disable I-cache and Branche predicotrs on non-armv7
         bic     r4, r4, #(1 << CP15_C1_IC)
         bic     r4, r4, #(1 << CP15_C1_BP)
+        
+        mcr     p15, 0, r4, c1, c0, 0
 #endif
-        mcr     p15, 0, r4, c1, c0, 0
+
 
         
@@ -82 +88 @@
         dsb
 #else
+        andi r4, 0
         #cp15 dsb, r4 is ignored (should be zero)
         mcr p15, 0, r4, c7, c10, 4

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -205 +205 @@
                 p->ns = 0;
         }
-        DCCMVAU_write((uint32_t)p);
+        DCCMVAC_write((uint32_t)p);
+        //TODO: DCCMVAU should be enough but it does not work.
 }
 
@@ -236 +237 @@
          * tex=0 buf=1 and cache=0 => shareable device mmio
          */
-        p->cacheable = (flags & PAGE_CACHEABLE);
+
+        if (flags & PAGE_CACHEABLE) {
+                p->tex = 1;
+                p->cacheable = 1;
+        } else {
+                p->tex = 0;
+                p->cacheable = 0;
+        }
         p->bufferable = 1;
-        p->tex = 0;
         
         /* Shareable is ignored for devices (non-cacheable),
          * turn it on for normal memory. */
-        p->shareable = 1;
+        p->shareable = 0;
         
         p->non_global = !(flags & PAGE_GLOBAL);
@@ -256 +263 @@
                         p->access_permission_1 = PTE_AP1_RO;
         }
-        DCCMVAU_write((uint32_t)p);
+        DCCMVAC_write((uint32_t)p);
+        //TODO: DCCMVAU should be enough but it does not work.
 }
 
@@ -267 +275 @@
         write_barrier();
         p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
-        DCCMVAU_write((uint32_t)p);
+        DCCMVAC_write((uint32_t)p);
+        //TODO: DCCMVAU should be enough but it does not work.
 }
 
@@ -275 +284 @@
 
         p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
-        DCCMVAU_write((uint32_t)p);
+        DCCMVAC_write((uint32_t)p);
+        //TODO: DCCMVAU should be enough but it does not work.
 }