Changeset 660e8fa in mainline for kernel/arch/arm32/include/barrier.h
- Timestamp:
- 2013-01-18T20:49:35Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 5fcd537, 6218d4b
- Parents:
- b5a3b50 (diff), a640bc1 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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kernel/arch/arm32/include/barrier.h
rb5a3b50 r660e8fa 39 39 /* 40 40 * TODO: implement true ARM memory barriers for macros below. 41 * ARMv6 introduced user access of the following commands: 42 * • Prefetch flush 43 * • Data synchronization barrier 44 * • Data memory barrier 45 * • Clean and prefetch range operations. 46 * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4 41 47 */ 42 48 #define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") 43 49 #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") 44 50 51 #if defined PROCESSOR_ARCH_armv7_a 52 /* ARMv7 uses instructions for memory barriers see ARM Architecture reference 53 * manual for details: 54 * DMB: ch. A8.8.43 page A8-376 55 * DSB: ch. A8.8.44 page A8-378 56 * See ch. A3.8.3 page A3-148 for details about memory barrier implementation 57 * and functionality on armv7 architecture. 58 */ 59 #define memory_barrier() asm volatile ("dmb" ::: "memory") 60 #define read_barrier() asm volatile ("dsb" ::: "memory") 61 #define write_barrier() asm volatile ("dsb st" ::: "memory") 62 #else 45 63 #define memory_barrier() asm volatile ("" ::: "memory") 46 64 #define read_barrier() asm volatile ("" ::: "memory") 47 65 #define write_barrier() asm volatile ("" ::: "memory") 48 66 #endif 49 67 /* 50 68 * There are multiple ways ICache can be implemented on ARM machines. Namely … … 62 80 */ 63 81 64 /* Available on both all supported arms, 82 #ifdef PROCESSOR_ARCH_armv7_a 83 #define smc_coherence(a) asm volatile ( "isb" ::: "memory") 84 #define smc_coherence_block(a, l) smc_coherence(a) 85 #else 86 /* Available on all supported arms, 65 87 * invalidates entire ICache so the written value does not matter. */ 88 //TODO might be PL1 only on armv5 - 66 89 #define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0") 67 90 #define smc_coherence_block(a, l) smc_coherence(a) 91 #endif 68 92 69 93
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