Changeset 235d31d in mainline for kernel/arch/sparc64/src/mm/sun4v/tlb.c

Timestamp:

2014-12-22T17:47:40Z (11 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8c7d5ad

Parents:

eae91e0 (diff), 759ea0d (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge the CHT pre-integration branch

This branch contains:

• the merge of lp:~adam-hraska+lp/helenos/rcu, which brings:

• a new preemptible kernel RCU variant called A-RCU,
• a preemptible variant of Podzimek's non-preemptible kernel RCU and
• a new variant of usersace RCU,
• a new concurrent hash table (CHT) implementation based on RCU,
• a deployment of CHT in kernel futex handling,
• a deployment of the userspace RCU in the implementation of upgradable futexes,

all described in Adam Hraska's master thesis named Read-Copy-Update
for HelenOS, defended in 2013 at MFF UK; furthemore, the branch
fixes two synchronization bugs in condvars and waitq, respectively:

• revid:adam.hraska+hos@gmail.com-20121116144921-3to9u1tn1sg07rg7
• revid:adam.hraska+hos@gmail.com-20121116173623-km7gwtqixwudpe66

• build fixes required to pass make check
• overhaul of ia64 and sparc64 trap handling, to allow exc_dispatch() to be used now when the kernel is more picky about CPU state accounting
• an important fix of the sparc64/sun4v preemptible trap handler
• various other fixes of issues discovered on non-x86 architectures

File:

• kernel/arch/sparc64/src/mm/sun4v/tlb.c (modified) (3 diffs)

kernel/arch/sparc64/src/mm/sun4v/tlb.c

@@ -208 +208 @@
 
 /** ITLB miss handler. */
-void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
+void fast_instruction_access_mmu_miss(unsigned int tt, istate_t *istate)
 {
         uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
@@ -239 +239 @@
  * low-level, assembly language part of the fast_data_access_mmu_miss handler.
  *
- * @param page_and_ctx  A 64-bit value describing the fault. The most
- *                      significant 51 bits of the value contain the virtual
- *                      address which caused the fault truncated to the page
- *                      boundary. The least significant 13 bits of the value
- *                      contain the number of the context in which the fault
- *                      occurred.
+ * @param tt            Trap type.
  * @param istate        Interrupted state saved on the stack.
  */
-void fast_data_access_mmu_miss(uint64_t page_and_ctx, istate_t *istate)
+void fast_data_access_mmu_miss(unsigned int tt, istate_t *istate)
 {
         pte_t *t;
-        uintptr_t va = DMISS_ADDRESS(page_and_ctx);
-        uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
+        uintptr_t va = DMISS_ADDRESS(istate->tlb_tag_access);
+        uint16_t ctx = DMISS_CONTEXT(istate->tlb_tag_access);
         as_t *as = AS;
 
@@ -288 +283 @@
 /** DTLB protection fault handler.
  *
- * @param page_and_ctx  A 64-bit value describing the fault. The most
- *                      significant 51 bits of the value contain the virtual
- *                      address which caused the fault truncated to the page
- *                      boundary. The least significant 13 bits of the value
- *                      contain the number of the context in which the fault
- *                      occurred.
+ * @param tt            Trap type.
  * @param istate        Interrupted state saved on the stack.
  */
-void fast_data_access_protection(uint64_t page_and_ctx, istate_t *istate)
+void fast_data_access_protection(unsigned int tt, istate_t *istate)
 {
         pte_t *t;
-        uintptr_t va = DMISS_ADDRESS(page_and_ctx);
-        uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
+        uintptr_t va = DMISS_ADDRESS(istate->tlb_tag_access);
+        uint16_t ctx = DMISS_CONTEXT(istate->tlb_tag_access);
         as_t *as = AS;