Changeset 235d31d in mainline for kernel/arch/ia32/src/smp/apic.c

Timestamp:

2014-12-22T17:47:40Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8c7d5ad

Parents:

eae91e0 (diff), 759ea0d (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge the CHT pre-integration branch

This branch contains:

• the merge of lp:~adam-hraska+lp/helenos/rcu, which brings:

• a new preemptible kernel RCU variant called A-RCU,
• a preemptible variant of Podzimek's non-preemptible kernel RCU and
• a new variant of usersace RCU,
• a new concurrent hash table (CHT) implementation based on RCU,
• a deployment of CHT in kernel futex handling,
• a deployment of the userspace RCU in the implementation of upgradable futexes,

all described in Adam Hraska's master thesis named Read-Copy-Update
for HelenOS, defended in 2013 at MFF UK; furthemore, the branch
fixes two synchronization bugs in condvars and waitq, respectively:

• revid:adam.hraska+hos@gmail.com-20121116144921-3to9u1tn1sg07rg7
• revid:adam.hraska+hos@gmail.com-20121116173623-km7gwtqixwudpe66

• build fixes required to pass make check
• overhaul of ia64 and sparc64 trap handling, to allow exc_dispatch() to be used now when the kernel is more picky about CPU state accounting
• an important fix of the sparc64/sun4v preemptible trap handler
• various other fixes of issues discovered on non-x86 architectures

File:

• kernel/arch/ia32/src/smp/apic.c (modified) (3 diffs)

kernel/arch/ia32/src/smp/apic.c

@@ -264 +264 @@
 }
 
-#define DELIVS_PENDING_SILENT_RETRIES   4       
-
+/* Waits for the destination cpu to accept the previous ipi. */
 static void l_apic_wait_for_delivery(void)
 {
         icr_t icr;
-        unsigned retries = 0;
-
+        
         do {
-                if (retries++ > DELIVS_PENDING_SILENT_RETRIES) {
-                        retries = 0;
-#ifdef CONFIG_DEBUG
-                        log(LF_ARCH, LVL_DEBUG, "IPI is pending.");
-#endif
-                        delay(20);
-                }
                 icr.lo = l_apic[ICRlo];
-        } while (icr.delivs == DELIVS_PENDING);
-        
+        } while (icr.delivs != DELIVS_IDLE);
+}
+
+/** Send one CPU an IPI vector.
+ *
+ * @param apicid Physical APIC ID of the destination CPU.
+ * @param vector Interrupt vector to be sent.
+ *
+ * @return 0 on failure, 1 on success.
+ */
+int l_apic_send_custom_ipi(uint8_t apicid, uint8_t vector)
+{
+        icr_t icr;
+
+        /* Wait for a destination cpu to accept our previous ipi. */
+        l_apic_wait_for_delivery();
+        
+        icr.lo = l_apic[ICRlo];
+        icr.hi = l_apic[ICRhi];
+        
+        icr.delmod = DELMOD_FIXED;
+        icr.destmod = DESTMOD_PHYS;
+        icr.level = LEVEL_ASSERT;
+        icr.shorthand = SHORTHAND_NONE;
+        icr.trigger_mode = TRIGMOD_LEVEL;
+        icr.vector = vector;
+        icr.dest = apicid;
+
+        /* Send the IPI by writing to l_apic[ICRlo]. */
+        l_apic[ICRhi] = icr.hi;
+        l_apic[ICRlo] = icr.lo;
+        
+        return apic_poll_errors();
 }
 
@@ -294 +316 @@
 {
         icr_t icr;
+
+        /* Wait for a destination cpu to accept our previous ipi. */
+        l_apic_wait_for_delivery();
         
         icr.lo = l_apic[ICRlo];
@@ -304 +329 @@
         
         l_apic[ICRlo] = icr.lo;
-
-        l_apic_wait_for_delivery();
         
         return apic_poll_errors();