Changeset 124bc22 in mainline for kernel/arch/mips32/include/arch/exception.h

Timestamp:

2019-04-04T18:08:51Z (5 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5d97627

Parents:

e064102

Message:

Reorganize interrupt and IRQ handling on mips32

This allows msim to use MIPS CPU interrupt numbers as IRQ numbers and
Malta to use ISA IRQ numbers as IRQ numbers. Common code can still
register MIPS CPU interrupts by their respective numbers.

File:

• kernel/arch/mips32/include/arch/exception.h (modified) (1 diff)

kernel/arch/mips32/include/arch/exception.h

@@ -57 +57 @@
 #define EXC_VCED   31
 
+#define INT_SW0    0
+#define INT_SW1    1
+#define INT_HW0    2
+#define INT_HW1    3
+#define INT_HW2    4
+#define INT_HW3    5
+#define INT_HW4    6
+#define INT_TIMER  7
+
+#define INTERRUPTS    8
+#define HW_INTERRUPTS (INTERRUPTS - 3)
+
+typedef void (* int_handler_t)(unsigned int);
+extern int_handler_t int_handler[];
+
 extern void exception(istate_t *istate);
 extern void tlb_refill_entry(void);