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Changeset 124bc22 in mainline


Ignore:
Timestamp:
2019-04-04T18:08:51Z (2 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master
Children:
5d97627
Parents:
e064102
Message:

Reorganize interrupt and IRQ handling on mips32

This allows msim to use MIPS CPU interrupt numbers as IRQ numbers and
Malta to use ISA IRQ numbers as IRQ numbers. Common code can still
register MIPS CPU interrupts by their respective numbers.

Location:
kernel/arch/mips32
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/mips32/include/arch/exception.h

    re064102 r124bc22  
    5757#define EXC_VCED   31
    5858
     59#define INT_SW0    0
     60#define INT_SW1    1
     61#define INT_HW0    2
     62#define INT_HW1    3
     63#define INT_HW2    4
     64#define INT_HW3    5
     65#define INT_HW4    6
     66#define INT_TIMER  7
     67
     68#define INTERRUPTS    8
     69#define HW_INTERRUPTS (INTERRUPTS - 3)
     70
     71typedef void (* int_handler_t)(unsigned int);
     72extern int_handler_t int_handler[];
     73
    5974extern void exception(istate_t *istate);
    6075extern void tlb_refill_entry(void);
  • kernel/arch/mips32/include/arch/mach/malta/malta.h

    re064102 r124bc22  
    3939#include <arch/machine_func.h>
    4040#include <arch/mm/page.h>
     41#include <typedefs.h>
    4142
    4243#define MALTA_PCI_BASE          PA2KSEG1(0x18000000UL)
     
    4748
    4849#define TTY_BASE                (MALTA_PCI_BASE + 0x3f8)
    49 #define TTY_CPU_INT             2
    5050#define TTY_ISA_IRQ             4
    5151
    52 #define GT64120_PCI0_INTACK     (MALTA_GT64120_BASE + 0xc34)
     52#define GT64120_PCI0_INTACK     ((ioport32_t *) (MALTA_GT64120_BASE + 0xc34))
    5353
    5454extern struct mips32_machine_ops malta_machine_ops;
  • kernel/arch/mips32/include/arch/machine_func.h

    re064102 r124bc22  
    4343
    4444#include <typedefs.h>
     45#include <stdbool.h>
    4546
    4647struct mips32_machine_ops {
  • kernel/arch/mips32/src/exception.c

    re064102 r124bc22  
    4747#include <symtab.h>
    4848#include <log.h>
     49#include <arch/machine_func.h>
    4950
    5051static const char *exctable[] = {
     
    174175
    175176        unsigned int i;
    176         for (i = 0; i < 8; i++) {
     177        for (i = 0; i < INTERRUPTS; i++) {
    177178
    178179                /*
     
    183184                 */
    184185                if (im & ip & (1 << i)) {
    185                         irq_t *irq = irq_dispatch_and_lock(i);
    186                         if (irq) {
    187                                 /*
    188                                  * The IRQ handler was found.
    189                                  */
    190                                 irq->handler(irq);
    191                                 if (irq->cir)
    192                                         irq->cir(irq->cir_arg, i);
    193                                 irq_spinlock_unlock(&irq->lock, false);
    194                         } else {
     186                        if (int_handler[i])
     187                                int_handler[i](i);
     188                        else {
    195189                                /*
    196190                                 * Spurious interrupt.
  • kernel/arch/mips32/src/interrupt.c

    re064102 r124bc22  
    4141#include <ipc/sysipc.h>
    4242
    43 #define IRQ_COUNT   8
    44 #define TIMER_IRQ   7
    45 
    46 function virtual_timer_fnc = NULL;
    47 static irq_t timer_irq;
    48 
    4943// TODO: This is SMP unsafe!!!
    5044
     
    5246static unsigned long nextcount;
    5347static unsigned long lastcount;
     48
     49/** Table of interrupt handlers. */
     50int_handler_t int_handler[INTERRUPTS] = {};
    5451
    5552/** Disable interrupts.
     
    113110}
    114111
    115 static irq_ownership_t timer_claim(irq_t *irq)
    116 {
    117         return IRQ_ACCEPT;
    118 }
    119 
    120 static void timer_irq_handler(irq_t *irq)
     112static void timer_interrupt_handler(unsigned int intr)
    121113{
    122114        if (cp0_count_read() < lastcount)
     
    135127        cp0_compare_write(nextcount);
    136128
    137         /*
    138          * We are holding a lock which prevents preemption.
    139          * Release the lock, call clock() and reacquire the lock again.
    140          */
    141         irq_spinlock_unlock(&irq->lock, false);
    142129        clock();
    143         irq_spinlock_lock(&irq->lock, false);
    144 
    145         if (virtual_timer_fnc != NULL)
    146                 virtual_timer_fnc();
    147130}
    148131
     
    150133void interrupt_init(void)
    151134{
    152         irq_init(IRQ_COUNT, IRQ_COUNT);
    153 
    154         irq_initialize(&timer_irq);
    155         timer_irq.inr = TIMER_IRQ;
    156         timer_irq.claim = timer_claim;
    157         timer_irq.handler = timer_irq_handler;
    158         irq_register(&timer_irq);
     135        int_handler[INT_TIMER] = timer_interrupt_handler;
    159136
    160137        timer_start();
    161         cp0_unmask_int(TIMER_IRQ);
     138        cp0_unmask_int(INT_TIMER);
    162139}
    163140
  • kernel/arch/mips32/src/mach/malta/malta.c

    re064102 r124bc22  
    4242#include <genarch/srln/srln.h>
    4343#include <arch/interrupt.h>
     44#include <stdbool.h>
     45#include <byteorder.h>
     46#include <log.h>
    4447
    4548static void malta_init(void);
     
    6871#endif
    6972
    70 #ifdef CONFIG_NS16550
    71 static void tty_clear_interrupt(void *arg, inr_t inr)
     73static void malta_isa_irq_handler(unsigned int i)
    7274{
    73         (void) pio_read_8((ioport8_t *) GT64120_PCI0_INTACK);
     75        uint8_t isa_irq = host2uint32_t_le(pio_read_32(GT64120_PCI0_INTACK));
     76        irq_t *irq = irq_dispatch_and_lock(isa_irq);
     77        if (irq) {
     78                irq->handler(irq);
     79                irq_spinlock_unlock(&irq->lock, false);
     80        } else {
     81#ifdef CONFIG_DEBUG
     82                log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious IRQ (irq=%u)",
     83                    CPU->id, isa_irq);
     84#endif
     85        }
    7486        pic_eoi();
    7587}
    76 #endif
    7788
    7889void malta_init(void)
    7990{
     91        irq_init(16, 16);
     92
    8093        i8259_init((i8259_t *) PIC0_BASE, (i8259_t *) PIC1_BASE, 2, 0, 8);
     94
     95        int_handler[INT_HW0] = malta_isa_irq_handler;
     96        cp0_unmask_int(INT_HW0);
    8197
    8298#if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
     
    86102        outdev_t **tty_out_ptr = NULL;
    87103#endif
    88         tty_instance = ns16550_init((ioport8_t *) TTY_BASE, 0, TTY_CPU_INT,
    89             tty_clear_interrupt, NULL, tty_out_ptr);
     104        tty_instance = ns16550_init((ioport8_t *) TTY_BASE, 0, TTY_ISA_IRQ,
     105            NULL, NULL, tty_out_ptr);
    90106#endif
    91107}
     
    121137                        ns16550_wire(tty_instance, srln);
    122138                        pic_enable_irqs(1 << TTY_ISA_IRQ);
    123                         cp0_unmask_int(TTY_CPU_INT);
    124139                }
    125140        }
  • kernel/arch/mips32/src/mach/msim/msim.c

    re064102 r124bc22  
    4141#include <genarch/drivers/dsrln/dsrlnout.h>
    4242#include <genarch/srln/srln.h>
     43#include <stdbool.h>
    4344
    4445static void msim_init(void);
     
    6061};
    6162
     63static void msim_irq_handler(unsigned int i)
     64{
     65        irq_t *irq = irq_dispatch_and_lock(i);
     66        if (irq) {
     67                irq->handler(irq);
     68                irq_spinlock_unlock(&irq->lock, false);
     69        } else {
     70#ifdef CONFIG_DEBUG
     71                log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious IRQ (irq=%u)",
     72                    CPU->id, i);
     73#endif
     74        }
     75}
     76
    6277void msim_init(void)
    6378{
     79        irq_init(HW_INTERRUPTS, HW_INTERRUPTS);
     80
     81        int_handler[INT_HW0] = msim_irq_handler;
     82        int_handler[INT_HW1] = msim_irq_handler;
     83        int_handler[INT_HW2] = msim_irq_handler;
     84        int_handler[INT_HW3] = msim_irq_handler;
     85        int_handler[INT_HW4] = msim_irq_handler;
     86
    6487        dorder_init();
    6588        cp0_unmask_int(MSIM_DDISK_IRQ);
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